component
XCF02SVOG20C
Public Made by Adomby adom
XILINX CPLD/FPGA, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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"package": "TSSOP-20",
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"digikey": "122-1287-5-ND",
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{
"number": "1",
"name": "D0",
"type": "tri_state",
"description": "DATA output pin providing data for configuring an FPGA in serial mode, set to high-impedance during ISPEN (when not clamped)."
},
{
"number": "2",
"name": "DNC",
"type": "unconnected",
"description": "Do not connect; this pin must be left unconnected."
},
{
"number": "3",
"name": "CLK",
"type": "input",
"description": "Configuration clock input; each rising edge increments the internal address counter if CLK is selected, CE is Low and OE/RESET is High."
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{
"number": "4",
"name": "TDI",
"type": "input",
"description": "JTAG serial data input to all instruction and data registers, with an internal 50 kΩ pull-up to VCCJ."
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{
"number": "5",
"name": "TMS",
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},
{
"number": "6",
"name": "TCK",
"type": "input",
"description": "JTAG test clock input that sequences the TAP controller and all JTAG test and programming electronics."
},
{
"number": "7",
"name": "CF",
"type": "output",
"description": "Configuration pulse open-drain output, pulsed Low by the JTAG CONFIG command to initiate FPGA configuration without powering down the FPGA."
},
{
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"name": "OE/RESET",
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"description": "Open-drain output enable/reset I/O; when Low it holds the address counter reset and DATA in high-impedance, and it is held Low during internal power-on reset."
},
{
"number": "9",
"name": "DNC",
"type": "unconnected",
"description": "Do not connect; this pin must be left unconnected."
},
{
"number": "10",
"name": "CE",
"type": "input",
"description": "Chip enable input; when High the device enters low-power standby, the address counter is reset and DATA pins are high-impedance."
},
{
"number": "11",
"name": "GND",
"type": "power_in",
"description": "Ground."
},
{
"number": "12",
"name": "DNC",
"type": "unconnected",
"description": "Do not connect; this pin must be left unconnected."
},
{
"number": "13",
"name": "CEO",
"type": "output",
"description": "Chip enable output connected to the CE input of the next PROM in the chain, Low when CE is Low, OE/RESET is High and the address counter is beyond its terminal count."
},
{
"number": "14",
"name": "DNC",
"type": "unconnected",
"description": "Do not connect; this pin must be left unconnected."
},
{
"number": "15",
"name": "DNC",
"type": "unconnected",
"description": "Do not connect; this pin must be left unconnected."
},
{
"number": "16",
"name": "DNC",
"type": "unconnected",
"description": "Do not connect; this pin must be left unconnected."
},
{
"number": "17",
"name": "TDO",
"type": "output",
"description": "JTAG serial data output for all instruction and data registers, with an internal 50 kΩ pull-up to VCCJ."
},
{
"number": "18",
"name": "VCCINT",
"type": "power_in",
"description": "+3.3V supply voltage for internal logic."
},
{
"number": "19",
"name": "VCCO",
"type": "power_in",
"description": "+3.3V, 2.5V, or 1.8V I/O supply connected to the output voltage drivers and input buffers."
},
{
"number": "20",
"name": "VCCJ",
"type": "power_in",
"description": "+3.3V or 2.5V JTAG I/O supply connected to the TDO output driver and TCK, TMS, and TDI input buffers."
}
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"at": "2026-10-23T03:06:42"
},
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"metadata": {
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"Package": "TSSOP-20",
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{
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{
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"name": "Electrostatic discharge",
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{
"name": "High-level output voltage for 3.3V outputs",
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"conditions": "IOH = –4 mA",
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{
"name": "Low-level output voltage for 2.5V outputs",
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{
"name": "Low-level output voltage for 1.8V outputs",
"symbol": "VOL",
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{
"name": "Internal voltage supply current, active mode",
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{
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{
"name": "JTAG supply current, active mode",
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{
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{
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{
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{
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},
{
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"min": -10,
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