component

TPS7350QP

Public Made by Adom

by adom

Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, PDIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)tps7350qpfactory-2.0.0extractor-text
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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs Publish 0.1.0 · Ray 22h ago
viewers tps7350qp: viewers · Ray 22h ago
package.json Publish 0.1.0 · Ray 22h ago
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README.md Initial commit: component/tps7350qp · Ray 22h ago
tps7350qp-etched.glb tps7350qp: factory component page (tier=lcsc) · Ray 22h ago
tps7350qp-etched.step tps7350qp: factory component page (tier=lcsc) · Ray 22h ago
tps7350qp-hero.glb tps7350qp: hero GLB from the etched model (keeps the MPN mark) · Ray 1h ago
tps7350qp-hero.overlay.json Publish 0.1.0 · Ray 22h ago
tps7350qp.glb Publish 0.1.0 · Ray 22h ago
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TPS7350QP

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · PDIP-8

TPS7350QP from Texas Instruments, in a PDIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground reference for the regulator.
2 EN input Enable input: a logic high shuts down the regulator into sleep mode (0.5 µA max quiescent at TJ = 25°C), and the pin is rated -0.3 V to 11 V.
3 IN power_in Unregulated input supply, rated -0.3 V to 11 V; tied internally in parallel with the other IN pin.
4 IN power_in Unregulated input supply, rated -0.3 V to 11 V; tied internally in parallel with the other IN pin.
5 OUT power_out Regulated 5-V output (4.9 V to 5.1 V) for 0 mA to 500 mA load current.
6 OUT power_out Regulated 5-V output (4.9 V to 5.1 V) for 0 mA to 500 mA load current.
7 SENSE input Output-voltage sense input for the fixed-voltage TPS7350, normally connected to OUT as close to the device as possible (pin is rated -0.3 V to 11 V).
8 RESET output Active-low open-drain NMOS reset output that stays low during an undervoltage condition on OUT and goes high after a 200-ms (typ) delay once it clears.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package PDIP-8
Category Power Management (PMIC)
Pins 8

CAD (KiCad official)

  • Symbol: TPS7350QP
  • Footprint: Package_DIP:DIP-8_W7.62mm
  • 3D model: PDIP-8 (KiCad packages3D, STEP)
  • 3D model files: tps7350qp-etched.step / tps7350qp-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps7350qp.step / tps7350qp.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (46 pp, sha256 64058afafde102b9, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF