component

TPS54427DDAR

Public Made by Adom

by adom

Texas Instruments DC-DC Converters, SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20260206
Name Last commit message Last updated
docs tps54427ddar: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
package.json Publish 0.2.0 · Ray 1mo ago
pads.json footprint: the shipped SOIC-8 has no thermal pad, but the symbol and the datasheet both show 9 pads. datasheet EP 2.71x3.4mm, TI DDA PowerPAD; TI's own land pattern. Chosen from this part's OWN datasheet, not inferred from a sibling - the Richtek SOP-8-EP parts alone carry three different exposed-pad sizes, so family inference would have been wrong. Rebuilds the .lbr, re-derives pin 1 and pads.json. · Ray 1mo ago
page.json tps54427ddar: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 19h ago
README.md tps54427ddar: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 19d ago
tps54427ddar-etched.fit.json tps54427ddar: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
tps54427ddar-etched.glb tps54427ddar: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
tps54427ddar-etched.step tps54427ddar: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
tps54427ddar.glb 3D: replace the model to match the corrected TI_SO-PowerPAD-8 footprint. The page shipped the plain SOIC-8 body, not the PowerPAD land, which no longer depicted the part after the footprint was fixed from its datasheet. Model is the exact one the new footprint references in the KiCad official library (CC-BY-SA 4.0), the same provenance page.json already records; .glb regenerated from it via service-step2glb. · Ray 1mo ago
tps54427ddar.kicad_mod footprint: the shipped SOIC-8 has no thermal pad, but the symbol and the datasheet both show 9 pads. datasheet EP 2.71x3.4mm, TI DDA PowerPAD; TI's own land pattern. Chosen from this part's OWN datasheet, not inferred from a sibling - the Richtek SOP-8-EP parts alone carry three different exposed-pad sizes, so family inference would have been wrong. Rebuilds the .lbr, re-derives pin 1 and pads.json. · Ray 1mo ago
tps54427ddar.kicad_sym Publish 0.1.0 · Ray 1mo ago
tps54427ddar.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect and oval pad as a SQUARE EAGLE smd; this carries the real pad shape across (0 -> 0 rounded pads) and stops dropping geometry drawn on KiCad User.N layers. Attributes, connects, pads and the pin-1 marker are gated against decreasing and are unchanged. · Ray 1mo ago
tps54427ddar.step 3D: replace the model to match the corrected TI_SO-PowerPAD-8 footprint. The page shipped the plain SOIC-8 body, not the PowerPAD land, which no longer depicted the part after the footprint was fixed from its datasheet. Model is the exact one the new footprint references in the KiCad official library (CC-BY-SA 4.0), the same provenance page.json already records; .glb regenerated from it via service-step2glb. · Ray 1mo ago

TPS54427DDAR

Texas Instruments · DC-DC Converters · SOP-8

TPS54427DDAR from Texas Instruments, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 EN input Enable input control. Active high; must be pulled up to enable the device. VIH ≥ 1.6 V, VIL ≤ 0.6 V. Internal ~450 kΩ pull-down to GND (225-900 kΩ). Absolute max −0.3 to 20 V.
2 VFB input Converter feedback input. Connect to the output voltage via a resistor divider to set VOUT. Internal reference (VFBTH) is 765 mV typ (757-773 mV at 25 °C). Input current ±0.1 µA max.
3 VREG5 power_out 5.5 V internal LDO power supply output (5.2-5.7 V, up to 60 mA). Bypass with a ~1 µF capacitor to GND. Not active when EN is low. Also feeds internal gate drive.
4 SS input Soft-start control. Connect an external capacitor from SS to GND to program the soft-start ramp time. Absolute max −0.3 to 6.5 V.
5 GND power_in Ground pin. Power ground return for the switching circuit. Sensitive SS and VFB returns must be tied to GND at a single point.
6 SW power_out Switch node between the high-side NFET (drain of low-side, source of high-side). Connect to the output inductor. Absolute max −2 to 20 V (−3 to 22 V for 10 ns transients).
7 VBST power_in Bootstrap supply for the high-side FET gate driver. Connect a 0.1 µF capacitor between VBST and SW. An internal diode is connected between VREG5 and VBST for charging. VBST(vs SW) max 6 V.
8 VIN power_in Input voltage supply pin. Operating range 4.5 V to 18 V (absolute max 20 V). Bypass with ceramic capacitance close to the pin.
9 PowerPAD power_in Exposed thermal pad on the underside. Must be soldered to the PCB ground plane for proper thermal dissipation and must be electrically connected to GND.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOP-8
Category PMIC
Pins 9

Ordering variants

Same part, different packaging or reel option.

  • TPS54427DDAR
  • TPS54427DDARDRC
  • TPS54427DDARDRCR

CAD (KiCad official)

  • Symbol: TPS54427DDAR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: tps54427ddar-etched.step / tps54427ddar-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps54427ddar.step / tps54427ddar.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
tps54427ddar.step 123 KB You want the bare part, or you mark your own boards.
tps54427ddar-etched.step 2.2 MB You want the part with TPS54427DDAR already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 558 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (32 pp, sha256 75b4634a9b5c2b51, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF