component
TPS54427DDAR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
main
Ray
tps54427ddar: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding)
91c4b80
1d ago
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{
"schema_version": 1,
"type": "component",
"slug": "tps54427ddar",
"title": "TPS54427DDAR",
"brief": "Texas Instruments DC-DC Converters, SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
"version": "0.2.0",
"license": "CC-BY-SA-4.0",
"tags": [
"component",
"pmic",
"tps54427ddar"
],
"component": {
"mpn": "TPS54427DDAR",
"manufacturer": "Texas Instruments",
"package": "SOP-8",
"pin_count": 9,
"category": "PMIC",
"subcategory": "DC-DC Converters",
"datasheet": "https://www.ti.com/lit/ds/symlink/tps54427ddar.pdf",
"parts": {
"symbol": "tps54427ddar.kicad_sym",
"footprint": "tps54427ddar.kicad_mod",
"model_3d": "tps54427ddar-etched.glb",
"model_3d_plain": "tps54427ddar.glb",
"model_3d_step": "tps54427ddar-etched.step",
"model_3d_step_plain": "tps54427ddar.step",
"lbr": "tps54427ddar.lbr"
},
"distributor_links": {
"lcsc": "C472488"
},
"pins": [
{
"number": "1",
"name": "EN",
"type": "input",
"description": "Enable input control. Active high; must be pulled up to enable the device. VIH ≥ 1.6 V, VIL ≤ 0.6 V. Internal ~450 kΩ pull-down to GND (225-900 kΩ). Absolute max −0.3 to 20 V."
},
{
"number": "2",
"name": "VFB",
"type": "input",
"description": "Converter feedback input. Connect to the output voltage via a resistor divider to set VOUT. Internal reference (VFBTH) is 765 mV typ (757-773 mV at 25 °C). Input current ±0.1 µA max."
},
{
"number": "3",
"name": "VREG5",
"type": "power_out",
"description": "5.5 V internal LDO power supply output (5.2-5.7 V, up to 60 mA). Bypass with a ~1 µF capacitor to GND. Not active when EN is low. Also feeds internal gate drive."
},
{
"number": "4",
"name": "SS",
"type": "input",
"description": "Soft-start control. Connect an external capacitor from SS to GND to program the soft-start ramp time. Absolute max −0.3 to 6.5 V."
},
{
"number": "5",
"name": "GND",
"type": "power_in",
"description": "Ground pin. Power ground return for the switching circuit. Sensitive SS and VFB returns must be tied to GND at a single point."
},
{
"number": "6",
"name": "SW",
"type": "power_out",
"description": "Switch node between the high-side NFET (drain of low-side, source of high-side). Connect to the output inductor. Absolute max −2 to 20 V (−3 to 22 V for 10 ns transients)."
},
{
"number": "7",
"name": "VBST",
"type": "power_in",
"description": "Bootstrap supply for the high-side FET gate driver. Connect a 0.1 µF capacitor between VBST and SW. An internal diode is connected between VREG5 and VBST for charging. VBST(vs SW) max 6 V."
},
{
"number": "8",
"name": "VIN",
"type": "power_in",
"description": "Input voltage supply pin. Operating range 4.5 V to 18 V (absolute max 20 V). Bypass with ceramic capacitance close to the pin."
},
{
"number": "9",
"name": "PowerPAD",
"type": "power_in",
"description": "Exposed thermal pad on the underside. Must be soldered to the PCB ground plane for proper thermal dissipation and must be electrically connected to GND."
}
],
"provenance": {
"extractor": "ds2sf",
"datasheet": {
"url": "https://www.ti.com/lit/ds/symlink/tps54427ddar.pdf",
"pages": 32,
"sha256": "75b4634a9b5c2b51",
"source_tier": "mfr"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 9,
"described": 9,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"pin1": {
"pad": "1",
"at": [
-2.475,
-1.905
],
"corner": "top-left",
"source": "silk-marker",
"derived_from": "SOIC-8_3.9x4.9mm_P1.27mm@sha256:074ecb2092b24fa4",
"mark": "drawn"
},
"models_3d": [
{
"file": "tps54427ddar.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
5.4,
4.9,
1.1
],
"zmin_mm": -0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "53b055ee4d166c0b9de551669cc1294f95b96baacbfe26d9316b576c1ce29fbf",
"checked": "2026-10-07",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "tps54427ddar-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
5.4,
4.9,
1.1
],
"zmin_mm": -0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "00f8b0186d75f562e5bc3def9b09fe7c52ba2cf9f1d988c819b7870ed085639e",
"checked": "2026-10-07",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
},
"metadata": {
"specs": {
"Manufacturer": "Texas Instruments",
"Package": "SOP-8",
"Category": "PMIC",
"Pins": "9"
}
},
"sections": [
"hero",
"viewers",
"readme",
"breadcrumbs",
"info"
],
"discovery_triggers": [
"tps54427ddar"
],
"discovery_pitch": "TPS54427DDAR (Texas Instruments) component page with datasheet-verified CAD.",
"author": {
"name": "Ray",
"email": "[email protected]"
},
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"tps54427ddar.kicad_sym",
"tps54427ddar.kicad_mod",
"tps54427ddar.glb",
"tps54427ddar.step",
"tps54427ddar-etched.step",
"tps54427ddar.lbr",
"docs/hero.png",
"docs/tps54427ddar-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html"
],
"visibility": {
"public": true
},
"variants": [
{
"mpn": "TPS54427DDAR",
"kind": "packaging"
},
{
"mpn": "TPS54427DDARDRC",
"kind": "packaging"
},
{
"mpn": "TPS54427DDARDRCR",
"kind": "packaging"
}
],
"updated_at": "2026-09-25T12:12:05.691Z"
}