component
TPS54340DDAR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, SOIC-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS54340DDAR
Texas Instruments · DC-DC Converters · SOIC-8-EP
TPS54340DDAR from Texas Instruments, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | power_out | Bootstrap voltage supply for high-side MOSFET gate driver; 0.1 µF ceramic capacitor (X5R or X7R, ≥10 V rating) required between BOOT and SW terminals. |
| 2 | VIN | power_in | Input supply voltage; operating range 4.5 V to 42 V with absolute maximum rating of 45 V and 10 ns transient rating of 45 V. |
| 3 | EN | input | Enable terminal with internal 1.2 µA pull-up current source; pull below 1.2 V enable threshold to disable device and reduce quiescent current to 1 µA. |
| 4 | RT/CLK | input | Resistor timing terminal for switching frequency set via external resistor to ground (100 kHz to 2500 kHz), or external clock synchronization input (160 kHz to 2300 kHz). |
| 5 | FB | input | Inverting input of transconductance error amplifier for output voltage feedback network; compared to internal 0.8 V ±1% reference. |
| 6 | COMP | output | Error amplifier output for frequency compensation network connection; internally clamped for peak current limit control of high-side MOSFET. |
| 7 | GND | power_in | Ground reference connection; must be electrically connected to thermal pad (pin 9) on PCB for proper operation. |
| 8 | SW | output | Switching node and source terminal of internal high-side MOSFET; connects to output inductor and catch diode with maximum voltage 45 V and transient rating of 45 V. |
| 9 | PowerPAD | power_in | Exposed thermal pad providing ground connection and thermal dissipation path; must be connected to PCB ground plane via multiple vias for proper thermal management and operation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |
CAD (KiCad official)
- Symbol:
TPS54340DDAR - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOIC-8-EP (KiCad packages3D, STEP)
- 3D model files:
tps54340ddar-etched.step/tps54340ddar-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps54340ddar.step/tps54340ddar.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (50 pp, sha256
3725db41574a827f, retrieved 2026-09-22, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).