# TPS5432DDAR

**Texas Instruments** · DC-DC Converters · HSOP-8-EP

TPS5432DDAR from Texas Instruments, in a HSOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | output | Bootstrap supply pin for high-side MOSFET gate drive; requires 0.1µF ceramic capacitor (X7R/X5R, ≥10V rating) connected between BOOT and PH. |
| 2 | VIN | power_in | Power supply input for control circuitry and power converter switches; operating range 2.95V to 6V. |
| 3 | PH | output | Phase switching node; source of high-side MOSFET and drain of low-side synchronous rectifier MOSFET. |
| 4 | GND | power_in | Ground reference; must be electrically connected directly to exposed thermal pad for proper operation. |
| 5 | VSENSE | input | Inverting input node to transconductance error amplifier; connected to output voltage feedback network via external resistor divider. |
| 6 | COMP | output | Error amplifier output and input to output switch current comparator; frequency compensation network connected to this pin. |
| 7 | EN | input | Enable control input with internal pull-up current source; pull to ground to disable switching and reduce quiescent current to ≤5µA. |
| 8 | SS | input | Slow start control input; external capacitor to ground sets the output voltage rise time during power-up. |
| 9 | THERMAL PAD | power_in | Exposed ground pad for thermal management; must be connected to internal PCB ground plane using multiple vias for proper thermal performance. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HSOP-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage VIN | VIN | -0.3 |  | 7 | V |  | 3 |
| Input voltage EN | EN | -0.3 |  | 3.6 | V |  | 3 |
| Input voltage BOOT (PH + 7) | BOOT |  |  | 7 | V |  | 3 |
| Input voltage VSENSE | VSENSE | -0.3 |  | 3 | V |  | 3 |
| Input voltage COMP | COMP | -0.3 |  | 3 | V |  | 3 |
| Input voltage SS | SS | -0.3 |  | 3 | V |  | 3 |
| Output voltage BOOT-PH | BOOT-PH |  |  | 7 | V |  | 3 |
| Output voltage PH | PH | -0.6 |  | 7 | V |  | 3 |
| Output voltage PH transient | PH | -2 |  | 10 | V | 10 ns transient | 3 |
| Source current EN |  |  |  | 100 | µA |  | 3 |
| Sink current COMP |  |  |  | 100 | µA |  | 3 |
| Sink current SS |  |  |  | 100 | µA |  | 3 |
| Electrostatic discharge (HBM) |  |  |  | 2 | kV | QSS 009-105 (JESD22-A114A) | 3 |
| Electrostatic discharge (CDM) |  |  |  | 500 | V | QSS 009-147 (JESD22-C101B.01) | 3 |
| Junction temperature | TJ | -40 |  | 150 | °C |  | 3 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 3 |
| Supply voltage | Vin | 2.95 |  | 6 | V | TJ = –40°C to 125°C | 4 |
| Shutdown quiescent current | Iq |  | 2 | 5 | µA | EN = 0V, 25°C, 2.95 V < Vin < 6 V | 4 |
| Operating quiescent current | Iq |  | 360 | 575 | µA | No load, Vin = 5 V, no switching, Vsense = 1 V, 25°C | 4 |
| Input UVLO threshold |  | 2.6 |  | 2.8 | V | Rising Vin | 4 |
| Enable threshold |  | 0.984 | 1.23 | 1.47 | V | Rising | 4 |
| Enable threshold |  | 0.952 |  | 1.19 | V | Falling | 4 |
| Voltage reference |  | 0.792 | 0.808 | 0.824 | V | 2.95 V < Vin < 6 V, TJ = 25°C | 4 |
| Voltage reference |  | 0.784 | 0.808 | 0.832 | V | 2.95 V < Vin < 6 V, –40°C < TJ < +125°C | 4 |
| H.S switch resistance |  | 62 |  | 86 | mΩ | BOOT-PH = 5 V, TJ = 25°C | 4 |
| L.S switch resistance |  | 73 |  | 103 | mΩ | Vin = 5 V, TJ = 25°C | 4 |
| H.S switch resistance |  | 88 |  | 114 | mΩ | BOOT-PH = 2.95 V, TJ = 25°C | 4 |
| L.S switch resistance |  | 94 |  | 128 | mΩ | Vin = 2.95 V, TJ = 25°C | 4 |
| High side current limit (I max) | I max | 3.8 | 5.7 | 7 | A | Vin = 3.3 V, duty cycle = 100% | 4 |
| Low side current limit (I max) | I max | 0.8 |  | 1.8 | A |  | 4 |
| Thermal shutdown |  | 155 |  | 170 | C |  | 4 |
| Switching frequency |  | 520 | 700 | 880 | kHz |  | 4 |
| Minimum on time |  | 120 |  | 150 | ns | Vin = 5 V; Measured at 50% points on PH, Iout = 3 A | 4 |
| Error amp source/sink |  | -20 |  | 20 | µA | V(COMP) = 1 V, 100 mV overdrive | 4 |
| UVLO hysteresis |  |  | 0.2 |  | V |  | 4 |
| Input current |  |  | -4.6 |  | µA | Enable threshold +50 mV | 4 |
| Input current |  |  | -1.2 |  | µA | Enable threshold –50 mV | 4 |
| Error amp transconductance (gm) | gm |  | 245 |  | µmho | –2 µA < ICOMP < 2 µA, V(COMP) = 1 V | 4 |
| Error amp transconductance (gm) during soft start | gm |  | 70 |  | µmho | –2 µA < ICOMP < 2 µA, V(COMP) = 1 V, Vsense = 0.3 V | 4 |
| COMP to Iph gm |  |  | 15 |  | A/V | Vin = 5 V, Iph1 = (0.5 or 1A) and Iph2 = 3 A | 4 |
| Vsense voltage for Fs foldback 50% frequency |  |  | 0.4 |  | V |  | 4 |
| Vsense voltage for Fs foldback 25% frequency |  |  | 0.2 |  | V |  | 4 |
| OT hysteresis |  |  | 15 |  | C |  | 4 |
| Minimum off time |  |  | 60 |  | ns | Prior to skipping off pulses, BOOT-PH = 2.95 V, Iout = 3 A | 4 |
| Rise/Fall time |  |  | 1.5 |  | V/ns | Vin = 5 V, Io = 0 A | 4 |
| Boot recharge FET resistance |  |  | 15 |  | Ω | Vin = 5 V | 4 |
| Boot UVLO |  |  | 2.1 |  | V | Vin = 2.95 V | 4 |
| Slow start charge current |  |  | 2 |  | μA | Vss = 0.4 V | 4 |
| Junction-to-ambient thermal resistance (θJA) | θJA |  | 42.1 |  | °C/W | DDA (8 pins) | 3 |
| Junction-to-case (top) thermal resistance (θJCtop) | θJCtop |  | 50.9 |  | °C/W | DDA (8 pins) | 3 |
| Junction-to-board thermal resistance (θJB) | θJB |  | 31.8 |  | °C/W | DDA (8 pins) | 3 |
| Junction-to-top characterization parameter (ψJT) | ψJT |  | 5 |  | °C/W | DDA (8 pins) | 3 |
| Junction-to-board characterization parameter (ψJB) | ψJB |  | 13.5 |  | °C/W | DDA (8 pins) | 3 |
| Junction-to-case (bottom) thermal resistance (θJCbot) | θJCbot |  | 7.1 |  | °C/W | DDA (8 pins) | 3 |

## CAD (KiCad official)

- Symbol: `TPS5432DDAR`
- Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm`
- 3D model: HSOP-8-EP (KiCad packages3D, STEP)
- 3D model files: `tps5432ddar-etched.step` / `tps5432ddar-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps5432ddar.step` / `tps5432ddar.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps5432) (33 pp, sha256 `e71b7195621bdd29`, retrieved 2026-09-22, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps5432ddar-datasheet.pdf)