TPS389001DSER

Texas Instruments TPS389001DSER is an adjustable voltage supervisor with a manual-reset input, active-low open-drain reset output and capacitor-programmable reset delay. It monitors voltages down to 1.15 V and comes in the 6-pin DSE WSON package with a nominal 1.5 x 1.5 mm body.

The reset output asserts when the sensed voltage falls below its threshold or the manual-reset input goes low. After both inputs recover, reset remains asserted for the programmed delay. Applications include power monitoring and reset sequencing for processors, programmable logic and other digital systems. See the manufacturer datasheet for operating limits and timing equations.

Pins

RESET requires an external pull-up. Select the sense divider, delay capacitor, pull-up voltage and local supply decoupling for the application using the datasheet. MR thresholds track VDD, so logic-level compatibility must be checked for the chosen supply.

Manufacturer sources

• TI datasheet and preserved local copy.
• TI family CAD page, the source of the original BXL and DSE0006A package model.
• Original manufacturer STEP, SHA-256 14a47e7abf178da4755a4bbc05c724ca531edd590029a97fa11f6ac0e67ff166.

Original manufacturer files are preserved unchanged. The Source field identifies the manufacturer; generation tools and display changes are recorded in the derivative manifests.

Reusable library assets

The symbol groups monitoring, control, reset and supply pins around the cached chip outline. The footprint includes a pin-1 silkscreen cue and separately recorded copper, mask and paste intent. The package has six terminals and no separate exposed pad.

Library qualification is incomplete. The manufacturer's model has leads 0.05 mm shorter than the drawing minimums measured in the recorded review. Display orientation does not resolve that discrepancy. Native seating, pin-1 registration, aperture export parity and manufacturing qualification remain separate checks. See the validation history and evidence before using the footprint or model for fabrication.

Annotated 3D model

The page displays TPS389001DSER.adom-reference-v2.glb. It uses the documented Adom Z-up pose, with the terminal floor at Z=0. The original source model is Y-thin; the separately named display derivative applies the recorded rigid transform once. See orientation provenance.

Reference artwork includes teal dashed pad boundaries at 50% transparency, silkscreen contours at 70% transparency and signal names at 50% transparency. These overlays are nonphysical inspection aids. The virtual TPS389001DSER marking occupies the reviewed clear top face and identifies the exact part; it does not claim to reproduce the factory marking. Original body and terminal geometry remain unchanged. See marking composition.

Cached chip artwork

Reuse the reviewed Z-up pose, MPN placement and vector outlines. Compare source hashes before reuse; cached display artwork does not qualify native seating or electrical connectivity.

Cache manifest and generation recipe

Component LODs

Four cached display levels retain the reviewed source pose. High and medium include the virtual MPN; low and super-low omit that fine detail. Cached images show each level without starting another 3D viewer. Turn on the optional preview to inspect detail changes as you zoom; turning it off releases its model and viewer resources. The table distinguishes display review from native qualification.

License and related projects

Original Adom-authored content is MIT licensed. Manufacturer and upstream files retain their original terms and attribution; see license scope.

TMF8829 Depth Lab is one consuming project. Board-specific circuit choices, sourcing snapshots and project progress belong there.

The component LOD downloads are clean board-use chip models. They retain actual package terminals and reviewed high/medium MPN markings, while excluding the footprint outlines, pad labels and silkscreen shown in the separate annotated wiki hero. The board EDA viewer supplies its own copper and silkscreen.