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TPS2399DGKR
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Texas Instruments Supervisor And Reset ICs, VSSOP-8-0.65mm. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TPS2399DGKR
Texas Instruments · Supervisor And Reset ICs · VSSOP-8-0.65mm
TPS2399DGKR from Texas Instruments, in a VSSOP-8-0.65mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PG | output | Open-drain, active-low power good output that is asserted only when the output is enabled, GATE has ramped to at least 7 V, and IRAMP exceeds about 5 V. |
| 2 | EN | input | Enable input referenced to -VIN; pulling it above the nominal 1.4-V threshold enables GATE and starts the load current ramp, while a low level disables the pass FET. |
| 3 | FLTTIME | bidirectional | Fault timeout programming pin; an external capacitor from FLTTIME to -VIN sets the fault timeout period, which is charged to the 4-V fault threshold during a fault. |
| 4 | IRAMP | bidirectional | Inrush slew rate programming pin; an external capacitor from IRAMP to -VIN sets the load current slew rate and is discharged when the output is disabled or a fault latches. |
| 5 | -VIN | power_in | Negative supply input and reference pin; the EN, ISENS, IRAMP and FLTTIME pins and all internal circuitry are referenced to it. |
| 6 | ISENS | input | Current sense input connected through a low-value sense resistor to -VIN; load current is regulated to a 40-mV reference, and a sense voltage above the 100-mV overload threshold pulls GATE low rapidly. |
| 7 | GATE | output | Gate drive output for the external N-channel pass FET, typically about 14 V when fully enhanced. |
| 8 | RTN | power_in | Positive supply input connected to the return node of the input power bus; the device is specified for input supply voltages of -36 V to -80 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VSSOP-8-0.65mm |
| Category | Power Management (PMIC) |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
TPS2399DGKR - Footprint:
Package_SO:VSSOP-8_2.3x2mm_P0.5mm - 3D model: VSSOP-8-0.65mm (KiCad packages3D, STEP)
- 3D model files:
tps2399dgkr-etched.step/tps2399dgkr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps2399dgkr.step/tps2399dgkr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (30 pp, sha256
2d3f49887517c851, retrieved 2026-10-08, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPS2399DGKR
**Texas Instruments** · Supervisor And Reset ICs · VSSOP-8-0.65mm
TPS2399DGKR from Texas Instruments, in a VSSOP-8-0.65mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PG | output | Open-drain, active-low power good output that is asserted only when the output is enabled, GATE has ramped to at least 7 V, and IRAMP exceeds about 5 V. |
| 2 | EN | input | Enable input referenced to -VIN; pulling it above the nominal 1.4-V threshold enables GATE and starts the load current ramp, while a low level disables the pass FET. |
| 3 | FLTTIME | bidirectional | Fault timeout programming pin; an external capacitor from FLTTIME to -VIN sets the fault timeout period, which is charged to the 4-V fault threshold during a fault. |
| 4 | IRAMP | bidirectional | Inrush slew rate programming pin; an external capacitor from IRAMP to -VIN sets the load current slew rate and is discharged when the output is disabled or a fault latches. |
| 5 | -VIN | power_in | Negative supply input and reference pin; the EN, ISENS, IRAMP and FLTTIME pins and all internal circuitry are referenced to it. |
| 6 | ISENS | input | Current sense input connected through a low-value sense resistor to -VIN; load current is regulated to a 40-mV reference, and a sense voltage above the 100-mV overload threshold pulls GATE low rapidly. |
| 7 | GATE | output | Gate drive output for the external N-channel pass FET, typically about 14 V when fully enhanced. |
| 8 | RTN | power_in | Positive supply input connected to the return node of the input power bus; the device is specified for input supply voltages of -36 V to -80 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VSSOP-8-0.65mm |
| Category | Power Management (PMIC) |
| Pins | 8 |
## CAD (KiCad official)
- Symbol: `TPS2399DGKR`
- Footprint: `Package_SO:VSSOP-8_2.3x2mm_P0.5mm`
- 3D model: VSSOP-8-0.65mm (KiCad packages3D, STEP)
- 3D model files: `tps2399dgkr-etched.step` / `tps2399dgkr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps2399dgkr.step` / `tps2399dgkr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/tps2399.pdf) (30 pp, sha256 `2d3f49887517c851`, retrieved 2026-10-08, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tps2399dgkr-datasheet.pdf)