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TPIC6595N

Public Made by Adom

by adom

Texas Instruments Shifting Register, PDIP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogic icstpic6595nfactory-2.0.0extractor-text

Verified TPIC6595N

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 20 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: TPIC6595N · PDIP-20 · 20 pins
  • ✓copper: 20 copper pads, none touching another net
  • ✓datasheet: all 20 pin names found in the 19-page datasheet
  • ✓distributor: lcsc C2861822, digikey 296-1954-5-ND, mouser 595-TPIC6595N
  • ✓family: DIP-20_W7.62mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-pvt42l8v/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 20 pins = 20 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 20 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ tpic6595n.kicad_sym✓ tpic6595n.kicad_mod✓ tpic6595n.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 15h ago
viewers tpic6595n: viewers · Ray 15h ago
package.json Publish 0.1.0 · Ray 15h ago
page.json Set visibility: public · Ray 15h ago
README.md Publish 0.1.0 · Ray 15h ago
tpic6595n-etched.glb Publish 0.1.0 · Ray 15h ago
tpic6595n-etched.step tpic6595n: factory component page (tier=mfr) · Ray 15h ago
tpic6595n-hero.glb tpic6595n: hero GLB from the etched model (keeps the MPN mark) · Ray 15h ago
tpic6595n-hero.overlay.json Publish 0.1.0 · Ray 15h ago
tpic6595n.glb Publish 0.1.0 · Ray 15h ago
tpic6595n.kicad_mod Publish 0.1.0 · Ray 15h ago
tpic6595n.kicad_sym Publish 0.1.0 · Ray 15h ago
tpic6595n.lbr Publish 0.1.0 · Ray 15h ago
tpic6595n.step Publish 0.1.0 · Ray 15h ago
verification.json Verified: Published by the parts factory: tier mfr, 20 pins · Ray 15h ago

TPIC6595N

Texas Instruments · Shifting Register · PDIP-20

TPIC6595N from Texas Instruments, in a PDIP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PGND power_in Power ground for the DMOS output drivers; internally connected to pins 10, 11, and 20 and must be externally connected to power system ground to minimize parasitic inductance.
2 VCC power_in Logic supply voltage, recommended 4.5 V to 5.5 V (absolute maximum 7 V with respect to LGND and PGND).
3 SER IN input Serial data input to the 8-bit shift register, clocked on the rising edge of SRCK with 10 ns minimum setup and hold times; logic-high input must be at least 0.85 VCC and logic-low at most 0.15 VCC.
4 DRAIN0 output Open-drain power DMOS sink output rated 45 V drain-to-source with 250 mA continuous sink current per output.
5 DRAIN1 output Open-drain power DMOS sink output rated 45 V drain-to-source with 250 mA continuous sink current per output.
6 DRAIN2 output Open-drain power DMOS sink output rated 45 V drain-to-source with 250 mA continuous sink current per output.
7 DRAIN3 output Open-drain power DMOS sink output rated 45 V drain-to-source with 250 mA continuous sink current per output.
8 SRCLR input Active-low shift-register clear: when low the input shift register is cleared, and when high the storage register transfers data to the output buffer.
9 G input Output enable: when held high all output buffer data is forced low and all drain outputs are off; when held low storage register data is transparent to the outputs.
10 PGND power_in Power ground; internally connected to pins 1, 11, and 20 and must be externally tied to power system ground.
11 PGND power_in Power ground; internally connected to pins 1, 10, and 20 and must be externally tied to power system ground.
12 RCK input Register clock; data transfers from the shift register to the 8-bit storage register on its rising edge.
13 SRCK input Shift-register clock; data transfers through the shift register on its rising edge, with 10 ns minimum setup and hold relative to SER IN and a 20 ns minimum pulse duration.
14 DRAIN4 output Open-drain power DMOS sink output rated 45 V drain-to-source with 250 mA continuous sink current per output.
15 DRAIN5 output Open-drain power DMOS sink output rated 45 V drain-to-source with 250 mA continuous sink current per output.
16 DRAIN6 output Open-drain power DMOS sink output rated 45 V drain-to-source with 250 mA continuous sink current per output.
17 DRAIN7 output Open-drain power DMOS sink output rated 45 V drain-to-source with 250 mA continuous sink current per output.
18 SER OUT output Serial data output from the shift register, provided to cascade data to additional devices.
19 LGND power_in Logic ground; must be connected in a single-point connection to power grounds pins 1, 10, 11, and 20 in a manner that reduces crosstalk between logic and load circuits.
20 PGND power_in Power ground; internally connected to pins 1, 10, and 11 and must be externally tied to power system ground.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package PDIP-20
Category Logic ICs
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Logic supply voltage VCC 4.5 5.5 V 4
High-level input voltage VIH 0.85 VCC 4
Low-level input voltage VIL 0.15 VCC 4
Pulsed drain output current -1.8 1.5 A TC = 25°C, VCC = 5 V (see Notes 3 and 5) 4
Setup time, SER IN high before SRCK↑ tsu 10 ns see Figure 2 4
Hold time, SER IN high after SRCK↑ th 10 ns see Figure 2 4
Pulse duration tw 20 ns see Figure 2 4
Operating case temperature TC -40 125 °C 4
Drain-source breakdown voltage V(BR)DSX 45 V ID = 1 mA 4
Source-drain diode forward voltage VSD 0.85 1 V IF = 250 mA, See Note 3 4
High-level output voltage VOH 4.4 4.49 V IOH = −20 mA, VCC = 4.5 V 4
High-level output voltage, SER OUT VOH 4.1 4.3 V IOH = −4 mA, VCC = 4.5 V 4
Low-level output voltage VOL 0.002 0.1 V IOH = 20 mA, VCC = 4.5 V 4
Low-level output voltage, SER OUT VOL 0.2 0.4 V IOH = 4 mA, VCC = 4.5 V 4
Input hysteresis V(hys) 1.3 V VDS = 15 V 4
High-level input current IIH 1 µA VCC = 5.5 V, VI = VCC 4
Low-level input current IIL -1 µA VCC = 5.5 V, VI = 0 4
Logic supply current ICCL 15 100 µA IO = 0, All inputs low 4
Logic supply current frequency ICC(FRQ) 0.6 5 mA fSRCK = 5 MHz, IO = 0, CL = 30 pF, See Figures 1, 2, and 6 4
Nominal current IN 250 mA VDS(on) = 0.5 V, IN = ID, TC = 85°C, See Notes 5, 6, and 7 4
Off-state drain current IDSX 0.05 1 µA VDS = 40 V 4
Off-state drain current IDSX 0.15 5 µA VDS = 40 V, TC = 125°C 4
Static drain-source on-state resistance rDS(on) 1.3 2 Ω ID = 250 mA, VCC = 4.5 V 4
Static drain-source on-state resistance rDS(on) 2 3.2 Ω ID = 250 mA, TC = 125°C, VCC = 4.5 V, See Notes 5 and 6 and Figures 9 and 10 4
Propagation delay time, low-to-high-level output from G tPLH 650 ns 4
Propagation delay time, high-to-low-level output from G tPHL 150 ns CL = 30 pF, ID = 250 mA 4
Rise time, drain output tr 750 ns CL = 30 pF, ID = 250 mA, See Figures 1 and 2 4
Fall time, drain output tf 425 ns See Figures 1 and 2 4
Reverse-recovery-current rise time ta 100 ns IF = 250 mA, di/dt = 20 A/µs 4
Reverse-recovery time trr 300 ns IF = 250 mA, di/dt = 20 A/µs, See Notes 5 and 6 and Figure 3 4
Logic supply voltage (absolute maximum) VCC 7 V See Note 1 3
Logic input voltage range VI -0.3 7 V 3
Power DMOS drain-to-source voltage VDS 45 V See Note 2 3
Continuous source-drain diode anode current 1 A 3
Pulsed source-drain diode anode current 2 A 3
Pulsed drain current, each output, all outputs on IDn 750 mA TA = 25°C (see Note 3) 3
Continuous drain current, each output, all outputs on IDn 250 mA TA = 25°C 3
Peak drain current single output IDM 2 A TA = 25°C (see Note 3) 3
Single-pulse avalanche energy EAS 75 mJ see Note 4 3
Avalanche current IAS 1 A see Note 4 3
Operating virtual junction temperature range TJ -40 150 °C 3
Storage temperature range Tstg -65 150 °C 3
Lead temperature 260 °C 1,6 mm (1/16 inch) from case for 10 seconds 3
Thermal resistance, junction-to-ambient (N package) RθJA 108 °C/W All 8 outputs with equal power 5
Power rating, N package 1150 mW TA ≤ 25°C 3
Power rating, N package 230 mW TA = 125°C 3

CAD (KiCad official)

  • Symbol: TPIC6595N
  • Footprint: Package_DIP:DIP-20_W7.62mm
  • 3D model: PDIP-20 (KiCad packages3D, STEP)
  • 3D model files: tpic6595n-etched.step / tpic6595n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tpic6595n.step / tpic6595n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (19 pp, sha256 fa207d32fc5054c8, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF