tp4056edtr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding)
tp4056edtr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero
Brief states the pinout check that actually ran (was an unconditional "Datasheet-verified pinout")
tp4056edtr: laser-etched CAD + chip hero (factory 2.0.0 backfill)
tp4056edtr: backfill missing artifacts (mfr, variants)
tp4056edtr: publish the laser-etched STEP alongside the bare one
fix ordering variants: suffix was duplicated into the MPN
rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an…
rebuild .lbr with adom-lbr 2.18.0: sanitises the pin name ['EXPOSED PAD'] EAGLE cannot carry, carries the F.SilkS pin-1…
add symbol pin "9" for the exposed thermal pad: the footprint carries the pad and the symbol had none, so it reached no…
pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left)
fix footprint: SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm -> SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm (3d refresh; body…
tp4056edtr: factory component page (tier=lcsc)
Initial commit: component/tp4056edtr