TP4056EDTR

@@ -0,0 +1,48 @@+# TP4056EDTR++**XBLW TP4056EDTR XBLW** · Battery Management · ESOP-8++TP4056EDTR from XBLW TP4056EDTR XBLW, in a ESOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | TEMP | input | Battery temperature sense input. Connects to the NTC divider on the battery pack; if V(TEMP) is below ~45% Vcc or above ~80% Vcc the charge cycle is suspended. Tie to GND to disable temperature qualification. |+| 2 | PROG | bidirectional | Charge-current program and monitor pin. Connect a resistor RPROG from PROG to GND to set IBAT = 1000 * VPROG / RPROG (±15%); the pin regulates to ~1V in constant-current mode and ~0.1V in trickle mode, and the voltage across RPROG can be measured to monitor actual charge current. |+| 3 | GND | power_in | Device ground. Electrically common with the exposed thermal pad on the bottom of the ESOP-8 package, which must be soldered to the PCB ground plane for proper heat dissipation. |+| 4 | VCC | power_in | Positive supply input (4.5V typ, 6.0V max; abs-max 7V). Supplies the internal circuitry and the pass PMOS to BAT. When VCC falls within ~30mV of VBAT, TP4056 enters a low-power sleep mode and BAT draws <2uA. |+| 5 | BAT | power_out | Battery connection. Sources up to ~1A of programmed charge current and regulates the float voltage to 4.2V (±1.5%). BAT leakage is <2uA when the chip is disabled or in sleep mode; abs-max continuous BAT current 1000mA. |+| 6 | STDBY | output | Open-drain charge-complete indicator (active-low, name is overbarred /STDBY). Pulled low by an internal switch when the charge cycle finishes; high-impedance otherwise. VOL ≤ 0.6V at 5mA sink. |+| 7 | CHRG | output | Open-drain charge-in-progress indicator (active-low, name is overbarred /CHRG). Pulled low by an internal switch while a charge cycle is active; high-impedance when charging is not in progress. VOL ≤ 0.6V at 5mA sink. |+| 8 | CE | input | Chip-enable input. Logic-high enables normal charging operation; logic-low disables charging and forces the device into a shutdown state. Compatible with TTL and CMOS logic levels; abs-max -0.3V to 8V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | XBLW TP4056EDTR XBLW |+| Package | ESOP-8 |+| Category | PMIC |+| Pins | 8 |++## Ordering variants++- `TP4056EDTREDTR`++## CAD (KiCad official)++- Symbol: `TP4056EDTR`+- Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm`+- 3D model: ESOP-8 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [XBLW TP4056EDTR XBLW datasheet](docs/tp4056edtr-datasheet.pdf) (15 pp, sha256 `0ba5d249802ce0d4`, retrieved 2026-08-17, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tp4056edtr-datasheet.pdf)

@@ -0,0 +1,34 @@+{+  "slug": "tp4056edtr",+  "version": "0.1.0",+  "type": "component",+  "description": "XBLW TP4056EDTR XBLW Battery Management, ESOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "pmic",+    "tp4056edtr"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "tp4056edtr.kicad_sym",+    "tp4056edtr.kicad_mod",+    "tp4056edtr.glb",+    "tp4056edtr.step",+    "tp4056edtr.lbr",+    "docs/hero.png",+    "docs/tp4056edtr-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "visibility": "public",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file