TP4056EDTR

@@ -1,13 +1,126 @@ {+  "schema_version": 1,+  "type": "component",   "slug": "tp4056edtr",+  "title": "TP4056EDTR",+  "brief": "XBLW TP4056EDTR XBLW Battery Management, ESOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",   "version": "0.1.0",-  "type": "component",-  "description": "XBLW TP4056EDTR XBLW Battery Management, ESOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "license": "CC-BY-SA-4.0",   "tags": [     "component",     "pmic",     "tp4056edtr"   ],+  "component": {+    "mpn": "TP4056EDTR",+    "manufacturer": "XBLW TP4056EDTR XBLW",+    "package": "ESOP-8",+    "pin_count": 8,+    "category": "PMIC",+    "subcategory": "Battery Management",+    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/e5f98a56063825c2e9998d7fe0e16aca.pdf",+    "parts": {+      "symbol": "tp4056edtr.kicad_sym",+      "footprint": "tp4056edtr.kicad_mod",+      "model_3d": "tp4056edtr.glb",+      "model_3d_step": "tp4056edtr.step",+      "lbr": "tp4056edtr.lbr"+    },+    "distributor_links": {},+    "pins": [+      {+        "number": "1",+        "name": "TEMP",+        "type": "input",+        "description": "Battery temperature sense input. Connects to the NTC divider on the battery pack; if V(TEMP) is below ~45% Vcc or above ~80% Vcc the charge cycle is suspended. Tie to GND to disable temperature qualification."+      },+      {+        "number": "2",+        "name": "PROG",+        "type": "bidirectional",+        "description": "Charge-current program and monitor pin. Connect a resistor RPROG from PROG to GND to set IBAT = 1000 * VPROG / RPROG (\u00b115%); the pin regulates to ~1V in constant-current mode and ~0.1V in trickle mode, and the voltage across RPROG can be measured to monitor actual charge current."+      },+      {+        "number": "3",+        "name": "GND",+        "type": "power_in",+        "description": "Device ground. Electrically common with the exposed thermal pad on the bottom of the ESOP-8 package, which must be soldered to the PCB ground plane for proper heat dissipation."+      },+      {+        "number": "4",+        "name": "VCC",+        "type": "power_in",+        "description": "Positive supply input (4.5V typ, 6.0V max; abs-max 7V). Supplies the internal circuitry and the pass PMOS to BAT. When VCC falls within ~30mV of VBAT, TP4056 enters a low-power sleep mode and BAT draws <2uA."+      },+      {+        "number": "5",+        "name": "BAT",+        "type": "power_out",+        "description": "Battery connection. Sources up to ~1A of programmed charge current and regulates the float voltage to 4.2V (\u00b11.5%). BAT leakage is <2uA when the chip is disabled or in sleep mode; abs-max continuous BAT current 1000mA."+      },+      {+        "number": "6",+        "name": "STDBY",+        "type": "output",+        "description": "Open-drain charge-complete indicator (active-low, name is overbarred /STDBY). Pulled low by an internal switch when the charge cycle finishes; high-impedance otherwise. VOL \u2264 0.6V at 5mA sink."+      },+      {+        "number": "7",+        "name": "CHRG",+        "type": "output",+        "description": "Open-drain charge-in-progress indicator (active-low, name is overbarred /CHRG). Pulled low by an internal switch while a charge cycle is active; high-impedance when charging is not in progress. VOL \u2264 0.6V at 5mA sink."+      },+      {+        "number": "8",+        "name": "CE",+        "type": "input",+        "description": "Chip-enable input. Logic-high enables normal charging operation; logic-low disables charging and forces the device into a shutdown state. Compatible with TTL and CMOS logic levels; abs-max -0.3V to 8V."+      }+    ],+    "provenance": {+      "extractor": "ds2sf",+      "datasheet": {+        "url": "https://datasheet.lcsc.com/datasheet/pdf/e5f98a56063825c2e9998d7fe0e16aca.pdf",+        "pages": 15,+        "sha256": "0ba5d249802ce0d4",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 8,+        "described": 8,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "metadata": {+    "specs": {+      "Manufacturer": "XBLW TP4056EDTR XBLW",+      "Package": "ESOP-8",+      "Category": "PMIC",+      "Pins": "8"+    }+  },+  "sections": [+    "hero",+    "viewers",+    "readme",+    "breadcrumbs",+    "info"+  ],+  "discovery_triggers": [+    "tp4056edtr"+  ],+  "discovery_pitch": "TP4056EDTR (XBLW TP4056EDTR XBLW) component page with datasheet-verified CAD.",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  },   "dependencies": {},   "hero": {     "type": "image",@@ -25,10 +138,5 @@     "docs/tp4056edtr-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ],-  "visibility": "public",-  "author": {-    "name": "Ray",-    "email": "[email protected]"-  }+  ] }\ No newline at end of file