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TMS320F2810PBKS

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Texas Instruments Digital Signal Processors (DSP/DSC), LQFP-128(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TMS320F2810PBKS

Texas Instruments · Digital Signal Processors (DSP/DSC) · LQFP-128(14x14)

TMS320F2810PBKS from Texas Instruments, in a LQFP-128(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDDAIO power_in 3.3-V analog I/O power pin.
2 ADCINB0 input ADC analog input B0 (Sample-and-Hold B); should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
3 ADCINB1 input ADC analog input B1 (Sample-and-Hold B); should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
4 ADCINB2 input ADC analog input B2 (Sample-and-Hold B); should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
5 ADCINB3 input ADC analog input B3 (Sample-and-Hold B); should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
6 ADCINB4 input ADC analog input B4 (Sample-and-Hold B); should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
7 ADCINB5 input ADC analog input B5 (Sample-and-Hold B); should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
8 ADCINB6 input ADC analog input B6 (Sample-and-Hold B); should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
9 ADCINB7 input ADC analog input B7 (Sample-and-Hold B); should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
10 ADCREFM bidirectional ADC 1-V voltage reference output (or external reference input if enabled in software); needs a low-ESR (under 1.5 ohm) 10 uF ceramic capacitor to analog ground.
11 ADCREFP bidirectional ADC 2-V voltage reference output (or external reference input if enabled in software); needs a low-ESR (under 1.5 ohm) 10 uF ceramic capacitor to analog ground.
12 AVSSREFBG power_in ADC analog ground.
13 AVDDREFBG power_in ADC analog power (3.3 V).
14 VDDA1 power_in ADC analog 3.3-V supply.
15 VSSA1 power_in ADC analog ground.
16 ADCRESEXT output ADC external current bias resistor: 24.9 kOhm ±5% for ADC clock 1-18.75 MHz, 20 kOhm ±5% for 18.75-25 MHz.
17 VSS power_in Core and digital I/O ground pin.
18 GPIOF13/MDRA bidirectional GPIO or McBSP received serial data input, with internal pullup.
19 GPIOF12/MDXA bidirectional GPIO or McBSP transmitted serial data output.
20 VDD power_in 1.8-V or 1.9-V core digital power pin.
21 GPIOF9/MCLKRA bidirectional GPIO or McBSP receive clock, with internal pullup.
22 GPIOF10/MFSXA bidirectional GPIO or McBSP transmit frame synch, with internal pullup.
23 GPIOF8/MCLKXA bidirectional GPIO or McBSP transmit clock, with internal pullup.
24 GPIOF11/MFSRA bidirectional GPIO or McBSP receive frame synch, with internal pullup.
25 VDDIO power_in 3.3-V I/O digital power pin.
26 VSS power_in Core and digital I/O ground pin.
27 GPIOF2/SPICLKA bidirectional GPIO or SPI clock.
28 GPIOF3/SPISTEA bidirectional GPIO or SPI slave transmit enable.
29 VDD power_in 1.8-V or 1.9-V core digital power pin.
30 VSS power_in Core and digital I/O ground pin.
31 GPIOF0/SPISIMOA bidirectional GPIO or SPI slave in, master out.
32 GPIOF1/SPISOMIA bidirectional GPIO or SPI slave out, master in.
33 GPIOB0/PWM7 bidirectional GPIO or PWM output pin #7, with internal pullup.
34 GPIOB1/PWM8 bidirectional GPIO or PWM output pin #8, with internal pullup.
35 GPIOB2/PWM9 bidirectional GPIO or PWM output pin #9, with internal pullup.
36 GPIOB3/PWM10 bidirectional GPIO or PWM output pin #10, with internal pullup.
37 GPIOB4/PWM11 bidirectional GPIO or PWM output pin #11, with internal pullup.
38 GPIOB5/PWM12 bidirectional GPIO or PWM output pin #12, with internal pullup.
39 VSS power_in Core and digital I/O ground pin.
40 GPIOB6/T3PWM_T3CMP bidirectional GPIO or Timer 3 output, with internal pullup.
41 GPIOB7/T4PWM_T4CMP bidirectional GPIO or Timer 4 output, with internal pullup.
42 VDD power_in 1.8-V or 1.9-V core digital power pin.
43 GPIOB8/CAP4_QEP3 bidirectional GPIO or capture input #4, with internal pullup.
44 GPIOB9/CAP5_QEP4 bidirectional GPIO or capture input #5, with internal pullup.
45 GPIOB10/CAP6_QEPI2 bidirectional GPIO or capture input #6, with internal pullup.
46 GPIOB13/C4TRIP bidirectional GPIO or Compare 4 output trip, with internal pullup.
47 GPIOB14/C5TRIP bidirectional GPIO or Compare 5 output trip, with internal pullup.
48 GPIOB15/C6TRIP bidirectional GPIO or Compare 6 output trip, with internal pullup.
49 VDDIO power_in 3.3-V I/O digital power pin.
50 TEST2 unconnected Test pin reserved for TI; must be left unconnected.
51 TEST1 unconnected Test pin reserved for TI; must be left unconnected.
52 VDD3VFL power_in 3.3-V flash core power pin; must be connected to 3.3 V at all times after power-up sequence requirements are met.
53 VSS power_in Core and digital I/O ground pin.
54 GPIOB11/TDIRB bidirectional GPIO or timer direction, with internal pullup.
55 GPIOB12/TCLKINB bidirectional GPIO or timer clock input, with internal pullup.
56 VDD power_in 1.8-V or 1.9-V core digital power pin.
57 X2 output Oscillator output.
58 X1/XCLKIN input Oscillator input or external clock input, referenced to the 1.8-V (or 1.9-V) core supply VDD rather than VDDIO; logic high must not exceed VDD.
59 VSS power_in Core and digital I/O ground pin.
60 GPIOD5/T3CTRIP_PDPINTB bidirectional GPIO or Timer 3 compare output trip, with internal pullup.
61 GPIOD6/T4CTRIP/EVBSOC bidirectional GPIO or Timer 4 compare output trip or external ADC start-of-conversion EV-B, with internal pullup.
62 VSS power_in Core and digital I/O ground pin.
63 VDD power_in 1.8-V or 1.9-V core digital power pin.
64 GPIOF6/CANTXA bidirectional GPIO or eCAN transmit data, with internal pullup.
65 GPIOF7/CANRXA bidirectional GPIO or eCAN receive data, with internal pullup.
66 GPIOG4/SCITXDB bidirectional GPIO or SCI-B asynchronous serial port transmit data.
67 GPIOG5/SCIRXDB bidirectional GPIO or SCI-B asynchronous serial port receive data.
68 GPIOA0/PWM1 bidirectional GPIO or PWM output pin #1, with internal pullup.
69 GPIOA1/PWM2 bidirectional GPIO or PWM output pin #2, with internal pullup.
70 GPIOA2/PWM3 bidirectional GPIO or PWM output pin #3, with internal pullup.
71 GPIOA3/PWM4 bidirectional GPIO or PWM output pin #4, with internal pullup.
72 GPIOA4/PWM5 bidirectional GPIO or PWM output pin #5, with internal pullup.
73 VSS power_in Core and digital I/O ground pin.
74 VDD power_in 1.8-V or 1.9-V core digital power pin.
75 GPIOA5/PWM6 bidirectional GPIO or PWM output pin #6, with internal pullup.
76 GPIOA6/T1PWM_T1CMP bidirectional GPIO or Timer 1 output, with internal pullup.
77 GPIOA7/T2PWM_T2CMP bidirectional GPIO or Timer 2 output, with internal pullup.
78 GPIOA8/CAP1_QEP1 bidirectional GPIO or capture input #1, with internal pullup.
79 GPIOA9/CAP2_QEP2 bidirectional GPIO or capture input #2, with internal pullup.
80 GPIOA10/CAP3_QEPI1 bidirectional GPIO or capture input #3, with internal pullup.
81 GPIOD0/T1CTRIP_PDPINTA bidirectional GPIO or Timer 1 compare output trip, with internal pullup.
82 VDD power_in 1.8-V or 1.9-V core digital power pin.
83 VDDIO power_in 3.3-V I/O digital power pin.
84 GPIOD1/T2CTRIP/EVASOC bidirectional GPIO or Timer 2 compare output trip or external ADC start-of-conversion EV-A, with internal pullup.
85 GPIOA11/TDIRA bidirectional GPIO or timer direction, with internal pullup.
86 GPIOA12/TCLKINA bidirectional GPIO or timer clock input, with internal pullup.
87 XCLKOUT output Output clock derived from SYSCLKOUT at the same, 1/2 or 1/4 frequency (1/4 at reset); not high-impedance during reset and can be turned off via CLKOFF bit.
88 VSS power_in Core and digital I/O ground pin.
89 GPIOA13/C1TRIP bidirectional GPIO or Compare 1 output trip, with internal pullup.
90 GPIOA14/C2TRIP bidirectional GPIO or Compare 2 output trip, with internal pullup.
91 GPIOA15/C3TRIP bidirectional GPIO or Compare 3 output trip, with internal pullup.
92 TMS input JTAG test-mode select with internal pullup, clocked into the TAP controller on the rising edge of TCK.
93 TDO tri_state JTAG test data output; selected register contents are shifted out on the falling edge of TCK.
94 VDD power_in 1.8-V or 1.9-V core digital power pin.
95 VSS power_in Core and digital I/O ground pin.
96 TDI input JTAG test data input with internal pullup, clocked into the selected register on the rising edge of TCK.
97 TESTSEL input Test pin reserved for TI with internal pulldown; must be connected to ground.
98 TRST input JTAG test reset with internal pulldown; active high, must be kept low during normal operation, no pullup resistors allowed.
99 TCK input JTAG test clock with internal pullup.
100 EMU0 bidirectional Emulator pin 0 with internal pullup; an external 2.2-kOhm to 4.7-kOhm pullup is recommended, also used for boundary-scan mode entry.
101 GPIOF14/XF_XPLLDIS bidirectional XF general-purpose output, GPIO, or XPLLDIS sampled during reset (PLL disabled if sensed low), with internal pullup.
102 VDD power_in 1.8-V or 1.9-V core digital power pin.
103 VSS power_in Core and digital I/O ground pin.
104 VDDIO power_in 3.3-V I/O digital power pin.
105 EMU1 bidirectional Emulator pin 1 with internal pullup; an external 2.2-kOhm to 4.7-kOhm pullup is recommended, also used for boundary-scan mode entry.
106 GPIOE0/XINT1_XBIO bidirectional GPIO or XINT1 or XBIO input.
107 GPIOE2/XNMI_XINT13 bidirectional GPIO or XNMI or XINT13, with internal pullup.
108 GPIOE1/XINT2_ADCSOC bidirectional GPIO or XINT2 or ADC start-of-conversion.
109 VSS power_in Core and digital I/O ground pin.
110 VDD power_in 1.8-V or 1.9-V core digital power pin.
111 GPIOF4/SCITXDA bidirectional GPIO or SCI-A asynchronous serial port TX data, with internal pullup.
112 GPIOF5/SCIRXDA bidirectional GPIO or SCI-A asynchronous serial port RX data, with internal pullup.
113 XRS bidirectional Device reset input and watchdog reset output (open-drain with internal 100-uA typical pullup); driven low for 512 XCLKIN cycles on watchdog reset.
114 VDD1 power_in ADC digital 1.8-V (or 1.9-V) supply.
115 VSS1 power_in ADC digital ground.
116 ADCBGREFIN unconnected Test pin reserved for TI; must be left unconnected.
117 VSSA2 power_in ADC analog ground.
118 VDDA2 power_in ADC analog 3.3-V supply.
119 ADCINA7 input ADC analog input A7 (Sample-and-Hold A); should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
120 ADCINA6 input ADC analog input A6 (Sample-and-Hold A); should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
121 ADCINA5 input ADC analog input A5 (Sample-and-Hold A); should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
122 ADCINA4 input ADC analog input A4 (Sample-and-Hold A); should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
123 ADCINA3 input ADC analog input A3 (Sample-and-Hold A); should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
124 ADCINA2 input ADC analog input A2 (Sample-and-Hold A); should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
125 ADCINA1 input ADC analog input A1 (Sample-and-Hold A); should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
126 ADCINA0 input ADC analog input A0 (Sample-and-Hold A); should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
127 ADCLO passive Common low-side analog input; connect to analog ground.
128 VSSAIO power_in Analog I/O ground pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-128(14x14)
Category Embedded Processors & Controllers
Pins 128

CAD (KiCad official)

  • Symbol: TMS320F2810PBKS
  • Footprint: Package_QFP:LQFP-128_14x14mm_P0.4mm
  • 3D model: LQFP-128(14x14) (KiCad packages3D, STEP)
  • 3D model files: tms320f2810pbks-etched.step / tms320f2810pbks-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms320f2810pbks.step / tms320f2810pbks.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (173 pp, sha256 3c891c6ecdaa247f, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF