TMC2262

"""Everything the two component pages say, with its datasheet citation. build.py turns this into the page folders.

Sources (both kept in datasheets/ and pushed to each page's docs/):
  LAN8770M: Microchip DS00002550C (LAN8770 100BASE-T1 Ethernet PHY Transceiver, Product Brief, 07-14-20), 26 pp.
  TMC2262:  Analog Devices TMC2262 data sheet Rev. 0 (02/26), 189 pp.; package outline 21-100708 Rev A;
            land pattern 90-100245 Rev B.
"""

SNAPSHOT = '2026-10-13'

LAN = dict(
    slug='lan8770m', mpn='LAN8770M-I/PRA', device='LAN8770M', mark='LAN8770M', lib_mpn='LAN8770M',
    title='LAN8770M',
    manufacturer='Microchip Technology', manufacturer_key='microchip',
    category='Interface', subcategory='Ethernet PHY transceiver (100BASE-T1, automotive Ethernet)',
    package='32-VQFN 5 x 5 x 0.85 mm, 0.5 mm pitch, wettable flanks (Microchip package code PRA)',
    package_short='32-VQFN (5x5), wettable flanks',
    body=dict(x_mm=5.0, y_mm=5.0, z_mm=0.85, pitch_mm=0.5), pin_count=33,
    visibility_public=False,
    brief='Microchip LAN8770M single-port 100BASE-T1 automotive Ethernet PHY with MII/RMII, 32-VQFN 5x5 wettable flank. '
          'KiCad, Fusion and Altium libraries, datasheet-built 3D model, every pin cited to the product brief.',
    one_liner='Single-port 100BASE-T1 (IEEE 802.3bw) automotive Ethernet PHY with MII and RMII host interfaces',
    hero_subhead='100BASE-T1 automotive Ethernet PHY, MII and RMII, 32-VQFN 5 x 5 mm',
    ds=dict(id='DS00002550C', title='LAN8770 100BASE-T1 Ethernet PHY Transceiver, Product Brief', rev='DS00002550C (07-14-20)',
            file='datasheets/lan8770-ds00002550c.pdf', url='https://ww1.microchip.com/downloads/en/DeviceDoc/LAN8770-Product-Brief-DS00002550C.pdf',
            pages=26),
    product_url='https://www.microchip.com/en-us/product/LAN8770',
    intro=[
        'The LAN8770 is Microchip\'s compact single-port 100BASE-T1 Ethernet physical layer transceiver, compliant with IEEE 802.3bw-2015. '
        'It sends and receives 100 Mbit/s over one unshielded twisted pair, for cable runs of at least 15 m, with PAM-3 line coding, '
        'echo cancellation and on-chip termination. The LAN8770M is the 32-pin family member: it talks to a MAC over MII or RMII '
        '(with a 50 MHz RMII reference clock output, or a 25 MHz / 50 MHz clock input), adds a reverse-MII mode for joining two PHYs back to back, '
        'and is configured over the SMI (MDIO/MDC) interface. The 36-pin LAN8770R adds RGMII and is a different package and land pattern, so it is not covered here.',
        'Power management follows OPEN Alliance TC10: an ultra-low-power sleep mode (12 uA typical), wake on the line or the WAKE_IN pin, an INH output that '
        'switches the ECU supply, and a dedicated ENABLE pin. Diagnostics include a signal quality indicator, cable open/short detection, over-temperature and '
        'under-voltage protection. The internal 1.1 V regulator feeds the core; VDDIO, VDD_XMII, VBAT, VDDA and VDDACOM take 1.8 V to 3.3 V or 2.5 V to 3.3 V supplies (DS00002550C pages 1, 3, 12 and 13).',
    ],
    doc_note='This page is built from Microchip\'s public product brief DS00002550C, which carries the pinout, pin descriptions, package drawing and land pattern. '
             'It does not carry the electrical characteristics, timing or register map: get the full LAN8770 data sheet from Microchip before you finish a design.',
    pin_table_pages='Table 2-1 (page 6) and Table 2-3 (pages 9 to 13)',
    groups_order=['Power', 'Ground', 'Line', 'Clock', 'SMI', 'Control', 'MII/RMII RX', 'MII/RMII TX'],
    group_desc={
        'Power': 'Five supply domains. VDDIO (SMI, RESET_N) and VDD_XMII (the MAC interface) take 1.8 V to 3.3 V; VBAT, VDDA (T1 analog front end) and VDDACOM (T1 common) take 2.5 V to 3.3 V. The two VDD11 pins are the 1.1 V core rail from the internal regulator: tie them together with 1 uF to ground (the LAN8770M regulator cannot be disabled).',
        'Ground': 'The exposed pad is the only ground (VSS). Connect it to the ground plane through a via array.',
        'Line': 'The 100BASE-T1 differential pair to the single twisted pair (through the usual common-mode choke and DC-blocking network), plus RBIAS, which needs 6.49 kOhm 0.1 % to ground.',
        'Clock': '25 MHz crystal between XTAL1 and XTAL2, or a single-ended oscillator into XTAL1/REFCLKIN with XTAL2 open (25 MHz, or 50 MHz in RMII clock-input mode).',
        'SMI': 'Serial Management Interface (MDIO/MDC) for register access, VDDIO domain.',
        'Control': 'ENABLE and WAKE_IN/INH run in the VBAT domain for TC10 sleep and wake; RESET_N (active low) and LED/IRQ_N (open drain) in the VDDIO domain.',
        'MII/RMII RX': 'Receive side of the MAC interface (VDD_XMII domain). Several pins double as configuration straps (MODE[3:0], PHYAD[1:0]) sampled at reset through internal 70 kOhm pull-downs. In RMII mode RXCLK/REFCLK is the 50 MHz reference clock output and RXD2/CRSDV carries CRS_DV.',
        'MII/RMII TX': 'Transmit side of the MAC interface (VDD_XMII domain). In RMII mode only TXD0, TXD1 and TXEN are used: ground TXD2 and TXD3, and TXCLK is unused.',
    },
    pins=[
        # number, name, KiCad type, group, description (DS00002550C Table 2-1 p6, Table 2-3 pp9-13, Table 2-4 p14)
        ('1', 'WAKE_IN', 'input', 'Control', 'Wake input (VIS-VBAT). Asserting it moves the PHY out of sleep; the optional wake input of the OPEN Alliance TC10 specification. VBAT domain.', 12),
        ('2', 'INH', 'output', 'Control', 'Inhibit output (VO-VBAT, open source, active high). Drives high in normal operation to keep the external supply on and goes high-Z in sleep to switch it off. Needs an external pull-down; RESET_N does not affect it.', 11),
        ('3', 'ENABLE', 'input', 'Control', 'Enable (AI). High enables the part; low puts it in its lowest-power DISABLE state. Must stay high during sleep. Pull up to VBAT, not VDDIO.', 11),
        ('4', 'MDIO', 'bidirectional', 'SMI', 'Serial Management Interface data input/output (VIS/VO-VDDIO).', 11),
        ('5', 'MDC', 'input', 'SMI', 'Serial Management Interface clock (VIS-VDDIO).', 11),
        ('6', 'VDDIO', 'power_in', 'Power', '+1.8 V to +3.3 V variable I/O supply for the SMI and control pins.', 12),
        ('7', 'VDD11', 'passive', 'Power', '+1.1 V digital core rail from the internal regulator. Tie both VDD11 pins (7 and 29) together with a 1 uF capacitor to ground. The LAN8770M regulator cannot be disabled.', 12),
        ('8', 'LED/IRQ_N', 'open_collector', 'Control', 'LED output (active low, open drain) or, by default, the device interrupt IRQ_N (active low, open drain). Float when unused.', 12),
        ('9', 'RESET_N', 'input', 'Control', 'System reset, active low (VIS-VDDIO). If unused, pull up to VDDIO.', 12),
        ('10', 'XTAL2', 'output', 'Clock', 'External 25 MHz crystal output (OCLK). Leave unconnected when XTAL1/REFCLKIN is driven by an oscillator.', 11),
        ('11', 'XTAL1/REFCLKIN', 'input', 'Clock', 'External 25 MHz crystal input, or single-ended clock input (ICLK): 25 MHz in every mode except RMII clock-input mode, which needs 50 MHz. 3.3 V tolerant.', 11),
        ('12', 'RXDV/MODE0', 'bidirectional', 'MII/RMII RX', 'MII receive data valid (VO-VDD_XMII); MODE0 configuration strap at reset (internal pull-down).', 10),
        ('13', 'RXCLK/REFCLK', 'output', 'MII/RMII RX', 'MII 25 MHz receive clock, or the 50 MHz RMII reference clock output to the MAC (VO-VDD_XMII).', 10),
        ('14', 'RXD3/MODE2', 'bidirectional', 'MII/RMII RX', 'Receive data bit 3 (MII; unused in RMII); MODE2 configuration strap at reset.', 9),
        ('15', 'RXD2/CRSDV/MODE1', 'bidirectional', 'MII/RMII RX', 'Receive data bit 2 (MII), or CRS_DV, carrier sense / receive data valid (RMII); MODE1 configuration strap at reset.', 10),
        ('16', 'RXD1/PHYAD0', 'bidirectional', 'MII/RMII RX', 'Receive data bit 1 (all modes); PHYAD0 address strap at reset.', 9),
        ('17', 'RXD0/MODE3', 'bidirectional', 'MII/RMII RX', 'Receive data bit 0 (all modes); MODE3 configuration strap at reset.', 9),
        ('18', 'RXER/PHYAD1', 'bidirectional', 'MII/RMII RX', 'Receive error (MII; optional in RMII); PHYAD1 address strap at reset.', 10),
        ('19', 'VDD_XMII', 'power_in', 'Power', '+1.8 V to +3.3 V variable supply for the MII/RMII interface pins; sets the MAC interface logic level.', 13),
        ('20', 'TXCLK', 'output', 'MII/RMII TX', 'MII 25 MHz transmit clock to the MAC (VO-VDD_XMII). Not used in RMII mode.', 9),
        ('21', 'TXEN', 'input', 'MII/RMII TX', 'Transmit enable: valid data on TXD (VIS-VDD_XMII). In RMII mode only TXD[1:0] carry data.', 9),
        ('22', 'TXD0', 'input', 'MII/RMII TX', 'Transmit data bit 0, all modes (VIS-VDD_XMII).', 9),
        ('23', 'TXD1', 'input', 'MII/RMII TX', 'Transmit data bit 1, all modes (VIS-VDD_XMII).', 9),
        ('24', 'TXD2', 'input', 'MII/RMII TX', 'Transmit data bit 2 (MII). Unused in RMII mode and must be grounded.', 9),
        ('25', 'TXD3', 'input', 'MII/RMII TX', 'Transmit data bit 3 (MII). Unused in RMII mode and must be grounded.', 9),
        ('26', 'VDDA', 'power_in', 'Power', '+2.5 V to +3.3 V supply for the 100BASE-T1 analog front end.', 13),
        ('27', 'TRXP', 'bidirectional', 'Line', 'Positive terminal of the 100BASE-T1 transmit/receive pair (AIO).', 11),
        ('28', 'TRXN', 'bidirectional', 'Line', 'Negative terminal of the 100BASE-T1 transmit/receive pair (AIO).', 11),
        ('29', 'VDD11', 'passive', 'Power', '+1.1 V digital core rail; tie to pin 7 (see pin 7).', 12),
        ('30', 'RBIAS', 'passive', 'Line', 'Reference resistor: connect 6.49 kOhm +/-0.1 % to ground.', 12),
        ('31', 'VDDACOM', 'power_in', 'Power', '+2.5 V to +3.3 V supply for the T1 common circuitry.', 13),
        ('32', 'VBAT', 'power_in', 'Power', '+2.5 V to +3.3 V supply for the always-on VBAT domain (WAKE_IN, INH, ENABLE).', 13),
        ('EP', 'VSS', 'power_in', 'Ground', 'Exposed pad: common ground. Must connect to the ground plane with a via array (Section 2.1 note, page 5; Table 2-3, page 13).', 13),
    ],
    specs=[
        ('Standard', 'IEEE 802.3bw-2015 100BASE-T1: 100 Mbit/s full duplex over one unshielded twisted pair, at least 15 m, PAM-3 coding, echo cancellation', 'DS00002550C pages 1 and 3'),
        ('MAC interface', 'MII or RMII (no RGMII on the LAN8770M); reverse MII for PHY-to-PHY links; SMI (MDIO/MDC) management', 'DS00002550C pages 1 and 3, Table 1-1 page 3'),
        ('RMII clocking', '50 MHz reference clock output on RXCLK/REFCLK, or 25 MHz / 50 MHz clock mode (REFCLKIN)', 'DS00002550C page 1; Table 2-3 pages 10 and 11'),
        ('Clock source', '25 MHz crystal on XTAL1/XTAL2, or a single-ended oscillator into XTAL1/REFCLKIN', 'DS00002550C Table 2-3 page 11'),
        ('Supplies', 'VDDIO and VDD_XMII 1.8 V to 3.3 V; VBAT, VDDA and VDDACOM 2.5 V to 3.3 V; internal 1.1 V core regulator (1 uF on VDD11)', 'DS00002550C Table 2-3 pages 12 and 13'),
        ('Low power', 'OPEN Alliance TC10 sleep and wake; ultra-low-power sleep 12 uA typical; WAKE_IN, INH and ENABLE pins', 'DS00002550C page 1'),
        ('Diagnostics', 'Signal quality indicator (SQI), cable open/short detection, over-temperature and under-voltage protection, loopback and test modes', 'DS00002550C pages 1 and 3'),
        ('Temperature grade (brief)', '-40 to +125 C, AEC-Q100 Grade 1 (E temperature code, -E/PRAVAO order codes)', 'DS00002550C pages 1, 3 and 23'),
        ('Package', '32-VQFN 5 x 5 x 0.85 mm (A 0.80 to 0.90), 0.50 mm pitch, exposed pad 3.10 mm, wettable flanks (step 0.125 mm high)', 'DS00002550C Figure 3-1 and 3-2, pages 16 and 17 (drawing C04-1268 Rev A)'),
        ('Land pattern', 'Contact span 4.90 mm, pads 0.30 x 0.85 mm, centre pad up to 3.20 mm, 9 thermal vias 0.33 mm on 1.20 mm pitch', 'DS00002550C Figure 3-3, page 18 (drawing C04-3268 Rev A)'),
    ],
    ordering=[
        # MPN, packing, temperature grade, note, source
        ('LAN8770M-I/PRA', 'Tray', 'I (industrial; distributors list -40 to +85 C)', 'The part this page ships as its MPN: stocked at Mouser, DigiKey and LCSC.', 'Mouser, DigiKey and LCSC listings, ' + '2026-10-13'),
        ('LAN8770MT-I/PRA', 'Tape and reel', 'I (industrial)', 'Same part on tape and reel.', 'Mouser and DigiKey listings, 2026-10-13'),
        ('LAN8770MT-V/PRA', 'Tape and reel', 'V (automotive variant; check Microchip for the range)', 'Listed by Mouser (no stock on 2026-10-13).', 'Mouser listing, 2026-10-13'),
        ('LAN8770M-E/PRAVAO', 'Tray', 'E, -40 to +125 C, AEC-Q100 Grade 1', 'Automotive order code from the product brief\'s identification system.', 'DS00002550C page 23'),
        ('LAN8770MT-E/PRAVAO', 'Tape and reel', 'E, -40 to +125 C, AEC-Q100 Grade 1', 'Automotive order code, tape and reel.', 'DS00002550C page 23'),
    ],
    ordering_note='Every row is the same 32-VQFN PRA package (drawing C04-1268) and land pattern (C04-3268), so the symbol, footprint and 3D model here fit all of them. '
                  'The I and V temperature codes are not described in the public product brief; their ranges come from the distributor listings, so confirm with Microchip before relying on them.',
    resources=[
        ('Product page (Microchip)', 'https://www.microchip.com/en-us/product/LAN8770', 'manufacturer authority: lifecycle, the full data sheet, errata, CAD and evaluation boards'),
        ('Product brief DS00002550C', 'https://ww1.microchip.com/downloads/en/DeviceDoc/LAN8770-Product-Brief-DS00002550C.pdf', 'the source of every pin, package dimension and land-pattern figure on this page (copy in docs/)'),
        ('EVB-LAN8770-RMII evaluation board (EV48S68A) user guide', 'https://www.mouser.com/datasheet/3/282/1/EVB_LAN8770_RMII_Evaluation_Board_Users_Guide_50002978A.pdf', 'Microchip reference design for the RMII connection to a MAC'),
        ('EVB-LAN8770M-MC converter board (EV02N47A) user guide', 'http://ww1.microchip.com/downloads/en/DeviceDoc/EVB-LAN8770M-MC-Eval-Board-User-Guide-50002979A.pdf', 'Microchip reference design using the LAN8770M'),
        ('Microchip packaging specification', 'http://www.microchip.com/packaging', 'the most current package drawings (C04-1268, C04-3268)'),
    ],
    figures=[(5, 'LAN8770M pin assignments (Figure 2-1)'), (6, 'Pin assignment table (Table 2-1)'), (9, 'Pin descriptions, MII/RMII (Table 2-3)'),
             (11, 'Pin descriptions, line, SMI and miscellaneous (Table 2-3)'), (12, 'Pin descriptions, reset, straps and power (Table 2-3)'),
             (16, 'Package drawing (Figure 3-1)'), (17, 'Package dimensions (Figure 3-2)'), (18, 'Land pattern (Figure 3-3)'), (23, 'Product identification system')],
    footprint_note='From the Microchip land pattern C04-3268 Rev A (DS00002550C Figure 3-3, page 18): 32 obround pads 0.30 x 0.85 mm on a 4.90 mm span at 0.50 mm pitch, '
                   'the 3.20 mm centre pad (the drawing\'s maximum) and its 3 x 3 grid of 0.33 mm thermal vias on 1.20 mm pitch. The paste on the centre pad is split into four '
                   '1.25 mm windows (61 % coverage); the land pattern does not specify a stencil, so this is the usual QFN practice, not a Microchip figure. '
                   'Microchip notes that thermal vias should be filled or tented.',
    model_note='No manufacturer 3D model was downloadable without a SamacSys or Ultra Librarian account, so the model is built from the package drawing C04-1268 Rev A '
               '(DS00002550C Figures 3-1 and 3-2) with CadQuery at nominal dimensions: body 5.00 x 5.00 x 0.85 mm, 32 terminals 0.25 x 0.40 mm with full-radius inner ends and the '
               '0.125 mm wettable-flank step, 3.10 mm exposed pad with its pin-1 chamfer, pin-1 dimple on the top. It is AI-generated from the drawing.',
    ep=dict(number='EP', name='VSS', w=3.20, h=3.20, drill=0.33, pitch=1.2, ring=0.15,
            note='The exposed pad is VSS, the only ground of the LAN8770M (DS00002550C page 5 and Table 2-3 page 13). The vias are Microchip\'s own: 9 x 0.33 mm on a 1.20 mm grid from the land pattern C04-3268 (page 18), filled or tented.'),
    related=[('STM32H563 (LQFP-64)', 'https://wiki.adom.inc/adom/stm32h563rgtx', 'an MCU with an Ethernet MAC whose RMII pins connect straight to this PHY')],
    tags=['component', 'ethernet', 'ethernet phy', '100base-t1', 'automotive ethernet', 'single pair ethernet', 'rmii', 'mii', 'microchip', 'lan8770', 'lan8770m', 'vqfn-32'],
    triggers=['LAN8770', 'LAN8770M', 'LAN8770M-I/PRA', '100BASE-T1 PHY', 'automotive ethernet PHY', 'single pair ethernet PHY', 'RMII 100BASE-T1'],
    distributors=dict(mouser='494-LAN8770M-I/PRA', digikey='150-LAN8770M-I/PRA-ND', lcsc='C5662322'),
)

TMC = dict(
    slug='tmc2262', mpn='TMC2262AFV+', device='TMC2262', mark='TMC2262AFV+', lib_mpn='TMC2262AFV+',
    title='TMC2262',
    manufacturer='Analog Devices', manufacturer_key='analog-devices',
    category='Motor driver', subcategory='Two-phase stepper motor driver with integrated MOSFETs (step/dir and SPI)',
    package='30-pin FC2QFN 6 x 6 x 0.75 mm, 0.5 mm pitch (ADI package code F306A6F+1F)',
    package_short='30L FC2QFN (6x6)',
    body=dict(x_mm=6.0, y_mm=6.0, z_mm=0.75, pitch_mm=0.5), pin_count=31,
    visibility_public=True,
    brief='Analog Devices TMC2262 65 V, 4 A RMS smart stepper driver with step/dir, SPI and encoder input, 30-pin FC2QFN 6x6. '
          'KiCad, Fusion and Altium libraries, datasheet-built 3D model, every pin cited to the data sheet.',
    one_liner='65 V, 4 A RMS (6 A peak) two-phase stepper motor driver with integrated current sensing, step/dir and SPI',
    hero_subhead='65 V, 4 A RMS smart stepper driver, step/dir and SPI, 30-pin FC2QFN 6 x 6 mm',
    ds=dict(id='TMC2262 Rev. 0', title='TMC2262 65V/4ARMS+ Fully Integrated Smart Stepper Motor Driver', rev='Rev. 0 (02/26)',
            file='datasheets/tmc2262.pdf', url='https://www.analog.com/media/en/technical-documentation/data-sheets/tmc2262.pdf', pages=189),
    product_url='https://www.analog.com/en/products/tmc2262.html',
    intro=[
        'The TMC2262 is a single-axis smart stepper motor driver from Analog Devices (Trinamic) with two integrated 65 V H-bridges rated 4 A RMS, 6 A full-scale sine peak and 9 A bridge peak, '
        'about 40 mOhm per MOSFET and lossless integrated current sensing, so no sense resistors are needed. It is aimed at NEMA 17, NEMA 23 and even NEMA 24 steppers. '
        'Motion comes in on a step and direction interface with up to 256 microsteps; configuration and diagnostics go over SPI (up to 8 MHz).',
        'StealthChop+ (silent voltage-mode chopper with resonance damping), SpreadCycle, StallGuard2 and StallGuard+ sensorless load detection, CoolStep and CoolStep+ current control, '
        'µDcStep and the TriCoder sensorless step-loss detection are on chip, alongside an incremental ABN encoder input, a temperature and supply-voltage ADC, an over-voltage output and '
        'the RT-OCSI real-time scope outputs. It runs from 4.5 V to 65 V with a 2.3 V to 5.5 V logic supply, in a thermally optimised 6 x 6 mm FC2QFN (TMC2262 data sheet Rev. 0, pages 1, 10 and 15).',
    ],
    doc_note='',
    pin_table_pages='Pin Descriptions (pages 16 and 17) and Figure 2 (page 18)',
    groups_order=['Motor supply', 'Ground', 'Coil A', 'Coil B', 'Charge pump', 'Logic supply', 'SPI', 'Step/Dir', 'Control', 'Diagnostics', 'Encoder'],
    group_desc={
        'Motor supply': 'Four VS pins feed both H-bridges, 4.5 V to 65 V (absolute maximum 70 V). Put filtering capacitance next to each pin with the shortest loop to the ground plane and exposed pad.',
        'Ground': 'GND pins 3 and 18 and the exposed die pad, which is the ground of the power stage and internal circuitry. Give the pad as many vias to the ground plane as possible.',
        'Coil A': 'H-bridge A outputs to one motor coil.',
        'Coil B': 'H-bridge B outputs to the other motor coil.',
        'Charge pump': 'High-side gate supply: 22 nF 100 V from CPI to CPO, 1.0 uF 10 V from VCP to VS.',
        'Logic supply': 'VCC_IO (2.3 V to 5.5 V) sets the digital I/O level; VDD is the internal 1.8 V regulator output and needs 2.2 uF or more to ground.',
        'SPI': 'Configuration and diagnostics, SPI mode with chip select active low, up to 8 MHz SCK; inputs have internal pull-downs.',
        'Step/Dir': 'Motion input: one microstep per STEP edge in the direction set by DIR.',
        'Control': 'DRV_ENN (high disables the power stage), SLEEPN (low puts the part to sleep and resets it), CLK (tie to GND for the internal 16 MHz clock) and IREF (current-scaling reference resistor, 12 kOhm nominal).',
        'Diagnostics': 'Two configurable outputs (open drain with a pull-up, or OCSI analog scope outputs). DO0 is held low during reset.',
        'Encoder': 'Incremental encoder inputs A, B and N. ENCN shares its pin with the active-low over-voltage output OVN.',
    },
    pins=[
        ('1', 'VS', 'power_in', 'Motor supply', 'Motor supply voltage. Provide filtering capacitance near the pin with the shortest loop to the GND plane and exposed pad.', 16),
        ('2', 'OA2', 'output', 'Coil A', 'Motor coil A output 2.', 16),
        ('3', 'GND', 'power_in', 'Ground', 'Ground. Connect to the ground plane.', 16),
        ('4', 'OA1', 'output', 'Coil A', 'Motor coil A output 1.', 16),
        ('5', 'VS', 'power_in', 'Motor supply', 'Motor supply voltage (see pin 1).', 16),
        ('6', 'VCP', 'passive', 'Charge pump', 'Charge pump voltage. Tie to VS with a 1.0 uF, 10 V capacitor.', 16),
        ('7', 'CPO', 'passive', 'Charge pump', 'Charge pump capacitor output.', 16),
        ('8', 'CPI', 'passive', 'Charge pump', 'Charge pump capacitor input. Tie to CPO with a 22 nF, 100 V capacitor.', 16),
        ('9', 'DIR', 'input', 'Step/Dir', 'Direction input.', 17),
        ('10', 'STEP', 'input', 'Step/Dir', 'Step input.', 17),
        ('11', 'CLK', 'input', 'Control', 'Clock input. Tie to GND with a short wire for the internal clock, or supply an external clock; an internal clock-fail-over circuit protects against loss of the external clock.', 16),
        ('12', 'CSN', 'input', 'SPI', 'SPI chip select input, active low (internal pull-down).', 16),
        ('13', 'SCK', 'input', 'SPI', 'SPI serial clock input (internal pull-down).', 16),
        ('14', 'SDI', 'input', 'SPI', 'SPI data input (internal pull-down).', 16),
        ('15', 'SDO', 'tri_state', 'SPI', 'SPI data output, tri-state (internal pull-down).', 16),
        ('16', 'VS', 'power_in', 'Motor supply', 'Motor supply voltage (see pin 1).', 16),
        ('17', 'OB1', 'output', 'Coil B', 'Motor coil B output 1.', 16),
        ('18', 'GND', 'power_in', 'Ground', 'Ground. Connect to the ground plane.', 16),
        ('19', 'OB2', 'output', 'Coil B', 'Motor coil B output 2.', 16),
        ('20', 'VS', 'power_in', 'Motor supply', 'Motor supply voltage (see pin 1).', 16),
        ('21', 'SLEEPN', 'input', 'Control', 'Low-active power-down and reset input. A continuous low puts the device to sleep; after sleep or reset it must be reconfigured (register contents are lost). Hold the bridges disabled with DRV_ENN while reconfiguring; do not use at high motor velocity. If unused, connect to VCC_IO. Internal pull-down.', 16),
        ('22', 'DO0', 'output', 'Diagnostics', 'Configurable output / diagnostics output 0 to the controller; use an external pull-up in open-drain mode. Pulled low during system reset. Can also be an on-chip scope (OCSI) analog output.', 16),
        ('23', 'ENCB', 'input', 'Encoder', 'Encoder B-channel input.', 16),
        ('24', 'ENCA', 'input', 'Encoder', 'Encoder A-channel input.', 16),
        ('25', 'VCC_IO', 'power_in', 'Logic supply', 'Digital I/O supply from an external source (2.3 V to 5.5 V); defines the I/O level and is required for correct output levels.', 17),
        ('26', 'VDD', 'power_out', 'Logic supply', 'Output of the internal 1.8 V regulator. Attach 2.2 uF or more ceramic to ground (AGND) near the pin.', 16),
        ('27', 'IREF', 'passive', 'Control', 'Analog reference current for current scaling: external resistor to GND (RREF, 12 kOhm in the electrical characteristics).', 16),
        ('28', 'ENCN/OVN', 'bidirectional', 'Encoder', 'Encoder N-channel input, or the over-voltage output (active low).', 16),
        ('29', 'DO1', 'output', 'Diagnostics', 'Configurable output / diagnostics output 1; external pull-up in open-drain mode. Can also be an OCSI analog output.', 16),
        ('30', 'DRV_ENN', 'input', 'Control', 'Enable input (internal pull-up). Driven high, the power stage is switched off and all motor outputs float.', 16),
        ('EP', 'GND', 'power_in', 'Ground', 'Exposed die pad: ground of the power stage and internal circuitry. Connect to a GND plane with as many vias as possible for heat transfer.', 16),
    ],
    specs=[
        ('Motor supply VS', '4.5 V to 65 V (absolute maximum 70 V)', 'Rev. 0 pages 1 and 10'),
        ('Output current', '4 A RMS (6 A full-scale sine peak) per H-bridge, 9 A bridge peak, typical at 25 C', 'Rev. 0 page 1'),
        ('RDS(on)', 'High side 0.040 ohm typ, low side 0.036 ohm typ (full-scale bits 11); 0.08 ohm HS + LS typical', 'Rev. 0 pages 1 and 11'),
        ('Current sensing', 'Fully integrated lossless current sensing (ICS); full-scale set by RREF on IREF (12 kOhm nominal)', 'Rev. 0 pages 1 and 12'),
        ('Interfaces', 'Step and direction (up to 256 microsteps, MicroPlyer interpolation); SPI up to 8 MHz; incremental ABN encoder input', 'Rev. 0 pages 1, 13 and 14'),
        ('Logic supply VCC_IO', '2.3 V to 5.5 V; internal 1.8 V VDD regulator', 'Rev. 0 page 10'),
        ('Clock', 'Internal 16 MHz oscillator (15.3 to 16.7 MHz) or external clock on CLK', 'Rev. 0 pages 12 and 13'),
        ('Protection', 'Overcurrent (10 A threshold at full-scale 11), VS UVLO 4 V, thermal shutdown 165 C with prewarning, short protection, over-voltage output', 'Rev. 0 pages 11 and 12'),
        ('Sleep current', 'IVS 10 uA maximum with SLEEPN low', 'Rev. 0 page 10'),
        ('Operating temperature', '-40 to +125 C', 'Rev. 0 pages 10 and 187'),
        ('Thermal', 'theta-JA 23 C/W (four-layer board, 4 W), theta-JC 2.6 C/W', 'Rev. 0 page 15'),
        ('Package', '30L FC2QFN 6 x 6 x 0.75 mm (F306A6F+1F), outline 21-100708, land pattern 90-100245', 'Rev. 0 page 15'),
    ],
    ordering=[
        ('TMC2262AFV+', 'Standard packing (not tape and reel)', '-40 to +125 C', 'The part this page ships as its MPN.', 'TMC2262 Rev. 0 page 187'),
        ('TMC2262AFV+T', 'Tape and reel', '-40 to +125 C', 'Same part on tape and reel ("T" denotes tape-and-reel).', 'TMC2262 Rev. 0 page 187'),
    ],
    ordering_note='Both order codes are the same 30L FC2QFN (F306A6F+1F) on the same land pattern, so the symbol, footprint and 3D model fit both. "+" denotes a lead-free, RoHS-compliant package.',
    resources=[
        ('Product page (Analog Devices)', 'https://www.analog.com/en/products/tmc2262.html', 'manufacturer authority: lifecycle, documentation, evaluation kit and the Symbols and Footprints downloads'),
        ('Data sheet TMC2262 Rev. 0', 'https://www.analog.com/media/en/technical-documentation/data-sheets/tmc2262.pdf', 'the source of every pin and specification on this page (copy in docs/)'),
        ('Package outline 21-100708 Rev A', 'https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/fc2qfn/21-100708a.pdf', 'the drawing the 3D model is built from (copy in docs/)'),
        ('Land pattern 90-100245 Rev B', 'https://www.analog.com/media/en/package-pcb-resources/land-pattern/fc2qfn/90-100245b.pdf', 'the drawing the footprint follows pad for pad (copy in docs/)'),
        ('TMC2262-EVKIT user guide', 'https://www.analog.com/media/en/technical-documentation/user-guides/tmc2262-evkit.pdf', 'ADI evaluation kit for this driver'),
    ],
    figures=[(1, 'Features and simplified block diagram'), (10, 'Absolute maximum ratings and power supply characteristics'), (11, 'Output and protection characteristics'),
             (15, 'Package information and marking'), (16, 'Pin descriptions'), (17, 'Pin descriptions (continued)'), (18, 'Pin configuration (Figure 2)'),
             (20, 'Block diagram with typical external components (Figure 4)'), (187, 'Ordering information')],
    footprint_note='From the ADI land pattern 90-100245 Rev B (package outline 21-100708 Rev A), pad for pad: ten 2.275 x 0.590 mm side bars, sixteen 0.300 x 0.725 mm pads, '
                   'four L-shaped corner pads (pins 6, 15, 21 and 30, drawn as KiCad custom pads with the drawing\'s R0.150 corner) and the 1.450 x 4.050 mm exposed pad, '
                   'all inside the 6.600 mm land-pattern extent. The data sheet asks for as many exposed-pad vias as possible; the footprint carries the Adom heatsink rule '
                   '(10 x 0.3 mm on a 0.7 mm grid, tented: the pitch that fits two columns on the 1.45 mm pad). The paste on the exposed pad is split into four 1.15 x 0.85 mm windows (66 %); ADI gives no stencil, so that is usual practice, not an ADI figure.',
    model_note='No manufacturer 3D model was downloadable without a SamacSys or Ultra Librarian account, so the model is built from the ADI package outline 21-100708 Rev A '
               'with CadQuery at nominal dimensions: body 6.00 x 6.00 x 0.75 mm, 0.203 mm lead frame, ten 0.54 x 1.95 mm side bars, sixteen 0.25 x 0.40 mm leads, four L-shaped '
               'corner terminals (b1 0.40, L1 0.65, L2 0.675), the 1.40 x 4.00 mm exposed pad with its C0.200 pin-1 chamfer, pin-1 dimple on the top. Terminal positions follow '
               'the land pattern 90-100245. It is AI-generated from the drawing.',
    ep=dict(number='EP', name='GND', w=1.45, h=4.05, drill=0.3, pitch=0.7, ring=0.15,
            note='The exposed die pad is GND for the power stage and internal circuitry; the data sheet asks for as many vias to the GND plane as possible (Pin Descriptions, page 16). '
                 'The array shown follows the Adom heatsink-via rule (0.3 mm drill, tented) on a 0.7 mm grid so two columns fit the 1.45 mm pad; it is not an ADI figure; theta-JA 23 C/W assumes a four-layer board (page 15).'),
    related=[('TMC2240ATJ+T', 'https://wiki.adom.inc/adom/tmc2240atj-t', 'the smaller 36 V, 2 A RMS sibling with SPI/UART and step/dir in a TQFN-32 5 x 5 mm')],
    tags=['component', 'motor driver', 'stepper driver', 'stepper motor', 'trinamic', 'analog devices', 'tmc2262', 'step dir', 'spi', 'stealthchop', 'fc2qfn'],
    triggers=['TMC2262', 'TMC2262AFV+', 'TMC2262AFV+T', '65V stepper driver', '4A stepper driver', 'Trinamic stepper driver', 'NEMA 23 stepper driver'],
    distributors=dict(mouser='700-TMC2262AFV+', digikey='175-TMC2262AFV+-ND', lcsc=None),
    lcsc_note='Not stocked by LCSC / JLCPCB: no listing found on 2026-10-13.',
)

PARTS = [LAN, TMC]