TMC2262

Analog Devices · 65 V, 4 A RMS (6 A peak) two-phase stepper motor driver with integrated current sensing, step/dir and SPI · 30L FC2QFN (6x6)

The TMC2262 is a single-axis smart stepper motor driver from Analog Devices (Trinamic) with two integrated 65 V H-bridges rated 4 A RMS, 6 A full-scale sine peak and 9 A bridge peak, about 40 mOhm per MOSFET and lossless integrated current sensing, so no sense resistors are needed. It is aimed at NEMA 17, NEMA 23 and even NEMA 24 steppers. Motion comes in on a step and direction interface with up to 256 microsteps; configuration and diagnostics go over SPI (up to 8 MHz).

StealthChop+ (silent voltage-mode chopper with resonance damping), SpreadCycle, StallGuard2 and StallGuard+ sensorless load detection, CoolStep and CoolStep+ current control, µDcStep and the TriCoder sensorless step-loss detection are on chip, alongside an incremental ABN encoder input, a temperature and supply-voltage ADC, an over-voltage output and the RT-OCSI real-time scope outputs. It runs from 4.5 V to 65 V with a 2.3 V to 5.5 V logic supply, in a thermally optimised 6 x 6 mm FC2QFN (TMC2262 data sheet Rev. 0, pages 1, 10 and 15).

Order code TMC2262AFV+ (standard packing (not tape and reel)). Datasheet: TMC2262 65V/4ARMS+ Fully Integrated Smart Stepper Motor Driver, Rev. 0 (02/26) (local copy: docs/tmc2262-datasheet.pdf). Product page: www.analog.com.

Manufacturer and resources

Everything on this page traces back to Analog Devices. Start here for the original documents and design resources.

Ordering variants

Both order codes are the same 30L FC2QFN (F306A6F+1F) on the same land pattern, so the symbol, footprint and 3D model fit both. "+" denotes a lead-free, RoHS-compliant package.

Pinout

Source: TMC2262 Rev. 0, Pin Descriptions (pages 16 and 17) and Figure 2 (page 18). Pin 1 is the top-left pad in the top view; the footprint marks it with a filled silkscreen dot and the 3D model with a dimple on the top.

Pin groups

The KiCad, Fusion and Altium symbols group the pins the same way:

• Motor supply: Four VS pins feed both H-bridges, 4.5 V to 65 V (absolute maximum 70 V). Put filtering capacitance next to each pin with the shortest loop to the ground plane and exposed pad.
• Ground: GND pins 3 and 18 and the exposed die pad, which is the ground of the power stage and internal circuitry. Give the pad as many vias to the ground plane as possible.
• Coil A: H-bridge A outputs to one motor coil.
• Coil B: H-bridge B outputs to the other motor coil.
• Charge pump: High-side gate supply: 22 nF 100 V from CPI to CPO, 1.0 uF 10 V from VCP to VS.
• Logic supply: VCC_IO (2.3 V to 5.5 V) sets the digital I/O level; VDD is the internal 1.8 V regulator output and needs 2.2 uF or more to ground.
• SPI: Configuration and diagnostics, SPI mode with chip select active low, up to 8 MHz SCK; inputs have internal pull-downs.
• Step/Dir: Motion input: one microstep per STEP edge in the direction set by DIR.
• Control: DRV_ENN (high disables the power stage), SLEEPN (low puts the part to sleep and resets it), CLK (tie to GND for the internal 16 MHz clock) and IREF (current-scaling reference resistor, 12 kOhm nominal).
• Diagnostics: Two configurable outputs (open drain with a pull-up, or OCSI analog scope outputs). DO0 is held low during reset.
• Encoder: Incremental encoder inputs A, B and N. ENCN shares its pin with the active-low over-voltage output OVN.

Key specifications

Sourcing

Snapshot 2026-10-13 (single-unit price and stock at that moment; check before ordering).

Not stocked by LCSC / JLCPCB: no listing found on 2026-10-13.

Packaging, handling and marking

• TMC2262AFV+ and TMC2262AFV+T (tape and reel); + marks a lead-free, RoHS-compliant package (Rev. 0 page 187).
• Top marking: ADI logo, part number (TMC + 2262), test flow and suffix, YYWW date code, assembly and fab code, and the lead-free + near pin 1 (Rev. 0 Figure 1 and Table 1, page 15).
• Absolute maximum: VS 70 V, VCC_IO 5.5 V, junction 160 C, reflow 260 C (Rev. 0 page 10).
• theta-JA 23 C/W on a four-layer board with 4 W dissipated: copper area and exposed-pad vias set how much current the part can run continuously (Rev. 0 page 15).

CAD

Adom-authored files are licensed CC-BY-4.0; the manufacturer documents in docs/ keep Analog Devices's terms.

3D models

No manufacturer 3D model was downloadable without a SamacSys or Ultra Librarian account, so the model is built from the ADI package outline 21-100708 Rev A with CadQuery at nominal dimensions: body 6.00 x 6.00 x 0.75 mm, 0.203 mm lead frame, ten 0.54 x 1.95 mm side bars, sixteen 0.25 x 0.40 mm leads, four L-shaped corner terminals (b1 0.40, L1 0.65, L2 0.675), the 1.40 x 4.00 mm exposed pad with its C0.200 pin-1 chamfer, pin-1 dimple on the top. Terminal positions follow the land pattern 90-100245. It is AI-generated from the drawing.

Footprint

From the ADI land pattern 90-100245 Rev B (package outline 21-100708 Rev A), pad for pad: ten 2.275 x 0.590 mm side bars, sixteen 0.300 x 0.725 mm pads, four L-shaped corner pads (pins 6, 15, 21 and 30, drawn as KiCad custom pads with the drawing's R0.150 corner) and the 1.450 x 4.050 mm exposed pad, all inside the 6.600 mm land-pattern extent. The data sheet asks for as many exposed-pad vias as possible; the footprint carries the Adom heatsink rule (10 x 0.3 mm on a 0.7 mm grid, tented: the pitch that fits two columns on the 1.45 mm pad). The paste on the exposed pad is split into four 1.15 x 0.85 mm windows (66 %); ADI gives no stencil, so that is usual practice, not an ADI figure.

Grey: the solderable faces of every terminal, read straight from the STEP. Teal dashed: every copper land of the footprint. Each terminal sits inside its land with the toe and heel the drawing gives, and pad 1 and the exposed-pad chamfer are top left. The full pad-by-pad comparison against the drawing is provenance/footprint-vs-datasheet.json (all lands match).

Fusion 360 and Altium: adom-lbr 2.47.5 cannot carry KiCad custom pads or paste-only windows yet, so the .lbr and the PcbLib draw each L-shaped corner pad as its two legs (two overlapping pads with the same number: identical copper except the R0.150 inner corner) and put paste over the whole exposed pad. Trim the exposed-pad paste in your stencil. Details in provenance/eda-lanes.json.

Thermal pad

The exposed die pad is GND for the power stage and internal circuitry; the data sheet asks for as many vias to the GND plane as possible (Pin Descriptions, page 16). The array shown follows the Adom heatsink-via rule (0.3 mm drill, tented) on a 0.7 mm grid so two columns fit the 1.45 mm pad; it is not an ADI figure; theta-JA 23 C/W assumes a four-layer board (page 15).

Chip outline cache

Provenance

Cited datasheet pages

Page images rendered from the TMC2262 Rev. 0 copy in docs/ (click to enlarge).

Talk to the AI

Paste one of these into an Adom AI thread:

• "Add the TMC2262 from the Adom wiki to my KiCad project and place it on the schematic."
• "Send the TMC2262 Fusion 360 library from the wiki to my desktop and open it."
• "Install the TMC2262 Altium library from adom/tmc2262 into my Altium project."
• "Lay out a TMC2262 stepper stage for a NEMA 17 at 24 V with the charge pump, VDD and IREF parts from the data sheet."

Related

• TMC2240ATJ+T - the smaller 36 V, 2 A RMS sibling with SPI/UART and step/dir in a TQFN-32 5 x 5 mm.

License

Adom-authored symbol, footprint, 3D models, artwork and scripts: CC-BY-4.0 (LICENSE). The datasheets and package drawings in docs/ are copyright Analog Devices and included for reference.