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STW68N60M6

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STMicroelectronics MOSFETs, TO-247-3. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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STW68N60M6

STMicroelectronics · MOSFETs · TO-247-3

STW68N60M6 from STMicroelectronics, in a TO-247-3. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G input Gate of the MDmesh M6 N-channel MOSFET; gate-source voltage is rated at ±25 V (absolute maximum, Table 1), and the part is Zener-protected.
2 D passive Drain, also connected to the mounting tab (D(2, TAB)); continuous drain current is 63 A at TC = 25 °C and 40 A at TC = 100 °C, with a 600 V drain-source breakdown voltage.
3 S passive Source of the MOSFET; source-drain diode continuous current is rated at 63 A (Table 7), with pulsed current limited to 252 A.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package TO-247-3
Category Triode/MOS Tube/Transistor
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Gate-source voltage VGS -25 25 V 2
Drain current (continuous) at TC = 25 °C ID 63 A TC = 25 °C 2
Drain current (continuous) at TC = 100 °C ID 40 A TC = 100 °C 2
Drain current (pulsed) IDM 252 A Pulse width limited by safe operating area 2
Total power dissipation at TC = 25 °C PTOT 390 W TC = 25 °C 2
Peak diode recovery voltage slope dv/dt(2) 15 V/ns ISD ≤ 63 A, di/dt ≤ 400 A/µs, VDD = 400 V 2
MOSFET dv/dt ruggedness dv/dt(3) 100 V/ns VDD ≤ 480 V 2
Storage temperature range Tstg -55 150 °C 2
Drain-source breakdown voltage V(BR)DSS 600 V VGS = 0 V, ID = 1 mA 3
Zero-gate voltage drain current IDSS 1 µA VGS = 0 V, VDS = 600 V 3
Zero-gate voltage drain current at TC = 125 °C IDSS 100 µA VGS = 0 V, VDS = 600 V, TC = 125 °C (specified by design, not tested in production) 3
Gate-body leakage current IGSS -5 5 µA VDS = 0 V, VGS = ±25 V 3
Gate threshold voltage VGS(th) 3.25 4 4.75 V VDS = VGS, ID = 250 µA 3
Static drain-source on-resistance RDS(on) 35 41 mΩ VGS = 10 V, ID = 31.5 A 3
Input capacitance Ciss 4360 pF VGS = 0 V, VDS = 100 V, f = 1 MHz 3
Output capacitance Coss 235 pF VGS = 0 V, VDS = 100 V, f = 1 MHz 3
Reverse transfer capacitance Crss 13 pF VGS = 0 V, VDS = 100 V, f = 1 MHz 3
Equivalent output capacitance Coss eq. 713 pF VGS = 0 V, VDS = 0 to 480 V 3
Intrinsic gate resistance Rg 1.6 Ω f = 1 MHz open drain 3
Total gate charge Qg 106 nC VDD = 480 V, ID = 63 A, VGS = 0 to 10 V 3
Gate-source charge Qgs 29 nC 3
Gate-drain charge Qgd 51 nC 3
Turn-on delay time td(on) 42 ns VDD = 300 V, ID = 30 A, RG = 4.7 Ω, VGS = 10 V 3
Rise time tr 28 ns 3
Turn-off delay time td(off) 130 ns 3
Fall time tf 8 ns 3
Source-drain current ISD 63 A 4
Source-drain current (pulsed) ISDM 252 A 4
Forward on voltage VSD 1.6 V VGS = 0 V, ISD = 63 A 4
Reverse recovery time trr 308 ns ISD = 63 A, di/dt = 100 A/µs, VDD = 60 V 4
Reverse recovery charge Qrr 4.3 µC ISD = 63 A, di/dt = 100 A/µs, VDD = 60 V 4
Reverse recovery current IRRM 26 A ISD = 63 A, di/dt = 100 A/µs, VDD = 60 V 4
Reverse recovery time at Tj = 150 °C trr 504 ns ISD = 63 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C 4
Reverse recovery charge at Tj = 150 °C Qrr 10.8 µC ISD = 63 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C 4
Reverse recovery current at Tj = 150 °C IRRM 38 A ISD = 63 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C 4
Thermal resistance, junction-to-case RthJC 0.32 °C/W 2
Thermal resistance, junction-to-ambient RthJA 50 °C/W 2
Avalanche current, repetitive or not repetitive IAR 7.5 A Pulse width limited by Tjmax 2
Single pulse avalanche energy EAS 1100 mJ Starting Tj = 25 °C, ID = IAR, VDD = 50 V 2

CAD (KiCad official)

  • Symbol: STW68N60M6
  • Footprint: Package_TO_SOT_THT:TO-247-3_Vertical
  • 3D model: TO-247-3 (KiCad packages3D, STEP)
  • 3D model files: stw68n60m6-etched.step / stw68n60m6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stw68n60m6.step / stw68n60m6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (12 pp, sha256 5f89dd69a438cf5a, retrieved 2026-10-12, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF