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STM8S001J3M3

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · SOP-8-150mil

STM8S001J3M3 from STMicroelectronics, in a SOP-8-150mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PD6/AIN6/UART1_RX/PA1/OSCIN bidirectional Multiplexed I/O bonding PD6 and PA1 to one pad; default functions are Port D6 (high-sink push-pull, O3 speed), AIN6 analog input, UART1 receive data, and PA1 external HSE clock input (0-16 MHz); note PA1 is forced to weak-pull-up in halt/active-halt modes.
2 VSS/VSSA power_in Digital ground and analog ground reference; both VSS and VSSA are bonded to this pin and must always be connected to the external power supply.
3 VCAP passive External capacitor node for the internal 1.8 V main voltage regulator; requires CEXT 470-3300 nF with ESR ≤ 0.3 Ω at 1 MHz and ESL ≤ 15 nH connected between this pin and VSS.
4 VDD/VDDA power_in Main power supply (2.95 V to 5.5 V) and analog supply/reference for the ADC; both VDD and VDDA are bonded to this pin and must always be connected to the external power supply.
5 PA3/TIM2_CH3/PB5/I2C_SDA bidirectional Multiplexed I/O bonding PA3 (high-sink push-pull, O3 speed) and PB5 (true open-drain, no P-buffer or pull-up to VDD); default functions Port A3/B5 with TIM2_CH3 and I2C_SDA (up to 400 kHz); PA3 remappable to SPI_NSS [AFR1] or UART1_TX [AFR1+AFR0], PB5 remappable to TIM1_BKIN [AFR4]; VIN max on this pin is limited by the standard PA3 GPIO.
6 PB4/I2C_SCL bidirectional Bidirectional I/O for PB4 as true open-drain (no P-buffer, no pull-up to VDD, no protection diode to VDD); default function I2C clock (up to 400 kHz); remappable to ADC external trigger [AFR4].
7 PC3/TIM1_CH3/PC4/CLK_CCO/TIM1_CH4/PC5/SPI_SCK bidirectional Multiplexed I/O bonding PC3, PC4, and PC5 to one pad (all high-sink push-pull, O3 speed); default functions Port C3/C4/C5 with TIM1_CH3, configurable clock output (CLK_CCO)/TIM1_CH4, and SPI_SCK; remappable to TLI [AFR3], AIN2 [AFR2], TIM2_CH1 [AFR0], TIM1_CH1N [AFR7], and TIM1_CH2N [AFR7]; push-pull configuration on any bonded GPIO affects all others on this pin.
8 PC6/SPI_MOSI/PD1/SWIM/PD3/AIN4/TIM2_CH2/PD5/AIN5/UART1_TX bidirectional Multiplexed I/O bonding PC6, PD1, PD3, and PD5 to one pad (all high-sink; PD1 O4 speed, others O3); PD1 is the SWIM single-wire debug interface and defaults to input pull-up during and after reset; other functions include SPI_MOSI, TIM1_CH1 [AFR0], AIN4/AIN5 analog inputs, TIM2_CH2, ADC_ETR, and UART1_TX; a ~5 s firmware delay before reassigning SWIM function is strongly recommended to allow reprogram access.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package SOP-8-150mil
Category Embedded Processors & Controllers
Pins 8

CAD (KiCad official)

  • Symbol: STM8S001J3M3
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8-150mil (KiCad packages3D, STEP)
  • 3D model files: stm8s001j3m3-etched.step / stm8s001j3m3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm8s001j3m3.step / stm8s001j3m3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (84 pp, sha256 64ae6cc93f3e51bc, retrieved 2026-09-26, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF