STM32G0B1KBU6

{
  "slug": "stm32g0b1kbu6",
  "version": "0.1.2",
  "type": "component",
  "tags": [
    "component",
    "embedded processors & controllers",
    "stm32g0b1kbu6",
    "board-derived"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "verification.json",
    "stm32g0b1kbu6.kicad_sym",
    "stm32g0b1kbu6.kicad_mod",
    "stm32g0b1kbu6-etched.glb",
    "stm32g0b1kbu6-etched.step",
    "stm32g0b1kbu6.glb",
    "stm32g0b1kbu6.step",
    "stm32g0b1kbu6.lbr",
    "docs/hero.png",
    "docs/stm32g0b1kbu6-datasheet.pdf",
    "provenance/3d-model.json",
    "provenance/tools/build.sh",
    "provenance/tools/kicad-generator-ds13560.patch",
    "provenance/tools/glbmat.py",
    "provenance/tools/ortho.py",
    "docs/proof/stm32g0b1kbu6-3d-model.png",
    "stm32g0b1kbu6-hero.glb",
    "stm32g0b1kbu6-hero.overlay.json"
  ],
  "component": {
    "mpn": "STM32G0B1KBU6",
    "manufacturer": "STMicroelectronics",
    "package": "UFQFPN-32(5x5)",
    "pin_count": 33,
    "category": "Embedded Processors & Controllers",
    "subcategory": "Microcontrollers",
    "datasheet": "https://www.st.com/resource/en/datasheet/stm32g0b1kb.pdf",
    "parts": {
      "symbol": "stm32g0b1kbu6.kicad_sym",
      "footprint": "stm32g0b1kbu6.kicad_mod",
      "model_3d": "stm32g0b1kbu6-hero.glb",
      "model_3d_plain": "stm32g0b1kbu6-etched.glb",
      "model_3d_step": "stm32g0b1kbu6-etched.step",
      "model_3d_step_plain": "stm32g0b1kbu6.step",
      "lbr": "stm32g0b1kbu6.lbr"
    },
    "distributor_links": {
      "digikey": {
        "part": "497-STM32G0B1KBU6-ND",
        "url": "https://www.digikey.com/en/products/detail/stmicroelectronics/STM32G0B1KBU6/18085531"
      },
      "mouser": {
        "part": "511-STM32G0B1KBU6",
        "url": "https://www.mouser.com/en/ProductDetail/STMicroelectronics/STM32G0B1KBU6?qs=CiayqK2gdcKiqlZpE0lOEQ%3D%3D"
      },
      "lcsc": {
        "part": "C5159549",
        "url": "https://www.lcsc.com/product-detail/C5159549.html"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "PB9",
        "type": "bidirectional",
        "description": "Port I/O PB9, I/O structure FT_f: 5 V tolerant, Fm+ capable [datasheet p.46]. Alternate functions: IR_OUT, UCPD2_FRSTX, TIM17_CH1, FDCAN1_TX, USART3_RX, SPI2_NSS/I2S2_WS, I2C1_SDA, EVENTOUT, USART6_RX, TIM4_CH4. Additional functions: none. [datasheet p.55]"
      },
      {
        "number": "2",
        "name": "PC14-OSC32_IN",
        "type": "bidirectional",
        "description": "Port I/O PC14-OSC32_IN, I/O structure FT: 5 V tolerant [datasheet p.46]. Alternate functions: TIM1_BKIN2. Additional functions: OSC32_IN, OSC_IN. [datasheet p.47] Supplied through the power switch (3 mA): as an output it is limited to 2 MHz with 30 pF and can sink but not source current; after an RTC domain power-up it operates as a GPIO whose function then depends on the RTC registers, which system reset does not reset (Table 12 notes 1-2). [datasheet p.55]"
      },
      {
        "number": "3",
        "name": "PC15-OSC32_OUT",
        "type": "bidirectional",
        "description": "Port I/O PC15-OSC32_OUT, I/O structure FT: 5 V tolerant [datasheet p.46]. Alternate functions: OSC32_EN, OSC_EN, TIM15_BKIN. Additional functions: OSC32_OUT. [datasheet p.47] Supplied through the power switch (3 mA): as an output it is limited to 2 MHz with 30 pF and can sink but not source current; after an RTC domain power-up it operates as a GPIO whose function then depends on the RTC registers, which system reset does not reset (Table 12 notes 1-2). [datasheet p.55]"
      },
      {
        "number": "4",
        "name": "VDD/VDDA",
        "type": "power_in",
        "description": "Supply pin (S) [datasheet p.47]. VDD 1.7 V to 3.6 V: external supply for the internal regulator, system analog and the I/Os (VDDIO1 = VDD); the same pin provides VDDA, the analog supply for the ADC, DAC, voltage reference buffer and comparators. On packages without the pin, VBAT is bonded to VDD/VDDA and VREF+ is connected to VDD (keep the voltage reference buffer disabled). [datasheet p.17]"
      },
      {
        "number": "5",
        "name": "VSS/VSSA",
        "type": "power_in",
        "description": "Supply pin (S): ground, VSS and VSSA on one pin. [datasheet p.47]"
      },
      {
        "number": "6",
        "name": "PF2-NRST",
        "type": "bidirectional",
        "description": "Port I/O PF2-NRST, I/O structure RST, FT: reset pin with embedded weak pull-up resistor; 5 V tolerant when used as GPIO [datasheet p.46]. Alternate functions: MCO, LPUART2_TX, LPUART2_RTS_DE. Additional functions: NRST. [datasheet p.48] RST I/O structure when configured as reset, FT when configured as GPIO (Table 12 note 3). [datasheet p.55]"
      },
      {
        "number": "7",
        "name": "PA0",
        "type": "bidirectional",
        "description": "Port I/O PA0, I/O structure FT_a: 5 V tolerant, analog switch function [datasheet p.46]. Alternate functions: SPI2_SCK/I2S2_CK, USART2_CTS, TIM2_CH1_ETR, USART4_TX, LPTIM1_OUT, UCPD2_FRSTX, COMP1_OUT. Additional functions: COMP1_INM8, ADC_IN0, TAMP_IN2, WKUP1. [datasheet p.48]"
      },
      {
        "number": "8",
        "name": "PA1",
        "type": "bidirectional",
        "description": "Port I/O PA1, I/O structure FT_ea: 5 V tolerant, switchable diode to VDDIOx, analog switch function [datasheet p.46]. Alternate functions: SPI1_SCK/I2S1_CK, USART2_RTS_DE_CK, TIM2_CH2, USART4_RX, TIM15_CH1N, I2C1_SMBA, EVENTOUT. Additional functions: COMP1_INP2, ADC_IN1. [datasheet p.48]"
      },
      {
        "number": "9",
        "name": "PA2",
        "type": "bidirectional",
        "description": "Port I/O PA2, I/O structure FT_a: 5 V tolerant, analog switch function [datasheet p.46]. Alternate functions: SPI1_MOSI/I2S1_SD, USART2_TX, TIM2_CH3, UCPD1_FRSTX, TIM15_CH1, LPUART1_TX, COMP2_OUT. Additional functions: COMP2_INM8, ADC_IN2, WKUP4, LSCO. [datasheet p.48]"
      },
      {
        "number": "10",
        "name": "PA3",
        "type": "bidirectional",
        "description": "Port I/O PA3, I/O structure FT_ea: 5 V tolerant, switchable diode to VDDIOx, analog switch function [datasheet p.46]. Alternate functions: SPI2_MISO/I2S2_MCK, USART2_RX, TIM2_CH4, UCPD2_FRSTX, TIM15_CH2, LPUART1_RX, EVENTOUT. Additional functions: COMP2_INP2, ADC_IN3. [datasheet p.49]"
      },
      {
        "number": "11",
        "name": "PA4",
        "type": "bidirectional",
        "description": "Port I/O PA4, I/O structure TT_a: 3.6 V tolerant, analog switch function [datasheet p.46]. Alternate functions: SPI1_NSS/I2S1_WS, SPI2_MOSI/I2S2_SD, USART6_TX, TIM14_CH1, LPTIM2_OUT, UCPD2_FRSTX, EVENTOUT, SPI3_NSS. Additional functions: ADC_IN4, DAC1_OUT1, TAMP_IN1, RTC_TS, RTC_OUT1, WKUP2. [datasheet p.49]"
      },
      {
        "number": "12",
        "name": "PA5",
        "type": "bidirectional",
        "description": "Port I/O PA5, I/O structure TT_ea: 3.6 V tolerant, switchable diode to VDDIOx, analog switch function [datasheet p.46]. Alternate functions: SPI1_SCK/I2S1_CK, CEC, TIM2_CH1_ETR, USART6_RX, USART3_TX, LPTIM2_ETR, UCPD1_FRSTX, EVENTOUT. Additional functions: ADC_IN5, DAC1_OUT2. [datasheet p.49]"
      },
      {
        "number": "13",
        "name": "PA6",
        "type": "bidirectional",
        "description": "Port I/O PA6, I/O structure FT_ea: 5 V tolerant, switchable diode to VDDIOx, analog switch function [datasheet p.46]. Alternate functions: SPI1_MISO/I2S1_MCK, TIM3_CH1, TIM1_BKIN, USART6_CTS, USART3_CTS, TIM16_CH1, LPUART1_CTS, COMP1_OUT, I2C2_SDA, I2C3_SDA. Additional functions: ADC_IN6. [datasheet p.49]"
      },
      {
        "number": "14",
        "name": "PA7",
        "type": "bidirectional",
        "description": "Port I/O PA7, I/O structure FT_a: 5 V tolerant, analog switch function [datasheet p.46]. Alternate functions: SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM1_CH1N, USART6_RTS_DE_CK, TIM14_CH1, TIM17_CH1, UCPD1_FRSTX, COMP2_OUT, I2C2_SCL, I2C3_SCL. Additional functions: ADC_IN7. [datasheet p.49]"
      },
      {
        "number": "15",
        "name": "PB0",
        "type": "bidirectional",
        "description": "Port I/O PB0, I/O structure FT_ea: 5 V tolerant, switchable diode to VDDIOx, analog switch function [datasheet p.46]. Alternate functions: SPI1_NSS/I2S1_WS, TIM3_CH3, TIM1_CH2N, FDCAN2_RX, USART3_RX, LPTIM1_OUT, UCPD1_FRSTX, COMP1_OUT, USART5_TX, LPUART2_CTS. Additional functions: COMP3_INP0, ADC_IN8. [datasheet p.50]"
      },
      {
        "number": "16",
        "name": "PB1",
        "type": "bidirectional",
        "description": "Port I/O PB1, I/O structure FT_ea: 5 V tolerant, switchable diode to VDDIOx, analog switch function [datasheet p.46]. Alternate functions: TIM14_CH1, TIM3_CH4, TIM1_CH3N, FDCAN2_TX, USART3_RTS_DE_CK, LPTIM2_IN1, LPUART1_RTS_DE, COMP3_OUT, USART5_RX, LPUART2_RTS_DE. Additional functions: COMP1_INM6, ADC_IN9. [datasheet p.50]"
      },
      {
        "number": "17",
        "name": "PB2",
        "type": "bidirectional",
        "description": "Port I/O PB2, I/O structure FT_ea: 5 V tolerant, switchable diode to VDDIOx, analog switch function [datasheet p.46]. Alternate functions: SPI2_MISO/I2S2_MCK, MCO2, USART3_TX, LPTIM1_OUT, EVENTOUT. Additional functions: COMP1_INP1, COMP3_INM6, ADC_IN10. [datasheet p.50]"
      },
      {
        "number": "18",
        "name": "PA8",
        "type": "bidirectional",
        "description": "Port I/O PA8, I/O structure FT_fcs: 5 V tolerant, Fm+ capable, USB Type-C PD capable, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: MCO, SPI2_NSS/I2S2_WS, TIM1_CH1, CRS1_SYNC, LPTIM2_OUT, EVENTOUT, I2C2_SMBA. Additional functions: UCPD1_CC1. [datasheet p.51] Table 12 note 4: upon reset a pull-down might be present on PA8, PB15, PD0 or PD2 depending on the voltage on PA9, PA10, PD1 and PD3 respectively; strobe the UCPDx_STROBE bits in SYSCFG_CFGR1 at start-up to disable it. [datasheet p.55]"
      },
      {
        "number": "19",
        "name": "PA9",
        "type": "bidirectional",
        "description": "Port I/O PA9, I/O structure FT_fds: 5 V tolerant, Fm+ capable, USB Type-C PD Dead Battery function, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: MCO, USART1_TX, TIM1_CH2, SPI2_MISO/I2S2_MCK, TIM15_BKIN, I2C1_SCL, EVENTOUT, I2C2_SCL. Additional functions: UCPD1_DBCC1. [datasheet p.51] Table 12 note 4: upon reset a pull-down might be present on PA8, PB15, PD0 or PD2 depending on the voltage on PA9, PA10, PD1 and PD3 respectively; strobe the UCPDx_STROBE bits in SYSCFG_CFGR1 at start-up to disable it. [datasheet p.55]"
      },
      {
        "number": "20",
        "name": "PC6",
        "type": "bidirectional",
        "description": "Port I/O PC6, I/O structure FT_s: 5 V tolerant, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: UCPD1_FRSTX, TIM3_CH1, TIM2_CH3, LPUART2_TX. Additional functions: none. [datasheet p.51]"
      },
      {
        "number": "21",
        "name": "PA10",
        "type": "bidirectional",
        "description": "Port I/O PA10, I/O structure FT_fds: 5 V tolerant, Fm+ capable, USB Type-C PD Dead Battery function, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: SPI2_MOSI/I2S2_SD, USART1_RX, TIM1_CH3, MCO2, TIM17_BKIN, I2C1_SDA, EVENTOUT, I2C2_SDA. Additional functions: UCPD1_DBCC2. [datasheet p.52] Table 12 note 4: upon reset a pull-down might be present on PA8, PB15, PD0 or PD2 depending on the voltage on PA9, PA10, PD1 and PD3 respectively; strobe the UCPDx_STROBE bits in SYSCFG_CFGR1 at start-up to disable it. [datasheet p.55]"
      },
      {
        "number": "22",
        "name": "PA11 [PA9]",
        "type": "bidirectional",
        "description": "Port I/O PA11 [PA9], I/O structure FT_fus: 5 V tolerant, Fm+ capable, USB function, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: SPI1_MISO/I2S1_MCK, USART1_CTS, TIM1_CH4, FDCAN1_RX, TIM1_BKIN2, I2C2_SCL, COMP1_OUT. Additional functions: USB_DM. [datasheet p.52] PA9/PA10 can be remapped in place of PA11/PA12 (default mapping) using SYSCFG_CFGR1 (Table 12 note 5). [datasheet p.55]"
      },
      {
        "number": "23",
        "name": "PA12 [PA10]",
        "type": "bidirectional",
        "description": "Port I/O PA12 [PA10], I/O structure FT_fus: 5 V tolerant, Fm+ capable, USB function, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: SPI1_MOSI/I2S1_SD, USART1_RTS_DE_CK, TIM1_ETR, FDCAN1_TX, I2S_CKIN, I2C2_SDA, COMP2_OUT. Additional functions: USB_DP. [datasheet p.52] PA9/PA10 can be remapped in place of PA11/PA12 (default mapping) using SYSCFG_CFGR1 (Table 12 note 5). [datasheet p.55]"
      },
      {
        "number": "24",
        "name": "PA13",
        "type": "bidirectional",
        "description": "Port I/O PA13, I/O structure FT_es: 5 V tolerant, switchable diode to VDDIOx, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: SWDIO, IR_OUT, USB_NOE, EVENTOUT, LPUART2_RX. Additional functions: none. [datasheet p.53] Upon reset configured as SW debug alternate function, with the internal pull-up on PA13 and pull-down on PA14 active (Table 12 note 6). [datasheet p.55]"
      },
      {
        "number": "25",
        "name": "PA14-BOOT0",
        "type": "bidirectional",
        "description": "Port I/O PA14-BOOT0, I/O structure FT_s: 5 V tolerant, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: SWCLK, USART2_TX, EVENTOUT, LPUART2_TX. Additional functions: BOOT0. [datasheet p.53] Upon reset configured as SW debug alternate function, with the internal pull-up on PA13 and pull-down on PA14 active (Table 12 note 6). [datasheet p.55]"
      },
      {
        "number": "26",
        "name": "PA15",
        "type": "bidirectional",
        "description": "Port I/O PA15, I/O structure FT_s: 5 V tolerant, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: SPI1_NSS/I2S1_WS, USART2_RX, TIM2_CH1_ETR, MCO2, USART4_RTS_DE_CK, USART3_RTS_DE_CK, USB_NOE, EVENTOUT, I2C2_SMBA, SPI3_NSS. Additional functions: none. [datasheet p.53]"
      },
      {
        "number": "27",
        "name": "PB3",
        "type": "bidirectional",
        "description": "Port I/O PB3, I/O structure FT_a: 5 V tolerant, analog switch function [datasheet p.46]. Alternate functions: SPI1_SCK/I2S1_CK, TIM1_CH2, TIM2_CH2, USART5_TX, USART1_RTS_DE_CK, I2C3_SCL, EVENTOUT, I2C2_SCL, SPI3_SCK. Additional functions: COMP2_INM6. [datasheet p.54]"
      },
      {
        "number": "28",
        "name": "PB4",
        "type": "bidirectional",
        "description": "Port I/O PB4, I/O structure FT_a: 5 V tolerant, analog switch function [datasheet p.46]. Alternate functions: SPI1_MISO/I2S1_MCK, TIM3_CH1, USART5_RX, USART1_CTS, TIM17_BKIN, I2C3_SDA, EVENTOUT, I2C2_SDA, SPI3_MISO. Additional functions: COMP2_INP0. [datasheet p.54]"
      },
      {
        "number": "29",
        "name": "PB5",
        "type": "bidirectional",
        "description": "Port I/O PB5, I/O structure FT: 5 V tolerant [datasheet p.46]. Alternate functions: SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM16_BKIN, FDCAN2_RX, LPTIM1_IN1, I2C1_SMBA, COMP2_OUT, USART5_RTS_DE_CK, SPI3_MOSI. Additional functions: WKUP6. [datasheet p.54]"
      },
      {
        "number": "30",
        "name": "PB6",
        "type": "bidirectional",
        "description": "Port I/O PB6, I/O structure FT_fa: 5 V tolerant, Fm+ capable, analog switch function [datasheet p.46]. Alternate functions: USART1_TX, TIM1_CH3, TIM16_CH1N, FDCAN2_TX, SPI2_MISO/I2S2_MCK, LPTIM1_ETR, I2C1_SCL, EVENTOUT, USART5_CTS, TIM4_CH1, LPUART2_TX. Additional functions: COMP2_INP1. [datasheet p.55]"
      },
      {
        "number": "31",
        "name": "PB7",
        "type": "bidirectional",
        "description": "Port I/O PB7, I/O structure FT_fa: 5 V tolerant, Fm+ capable, analog switch function [datasheet p.46]. Alternate functions: USART1_RX, SPI2_MOSI/I2S2_SD, TIM17_CH1N, USART4_CTS, LPTIM1_IN2, I2C1_SDA, EVENTOUT, TIM4_CH2, LPUART2_RX. Additional functions: COMP2_INM7, PVD_IN. [datasheet p.55]"
      },
      {
        "number": "32",
        "name": "PB8",
        "type": "bidirectional",
        "description": "Port I/O PB8, I/O structure FT_f: 5 V tolerant, Fm+ capable [datasheet p.46]. Alternate functions: CEC, SPI2_SCK/I2S2_CK, TIM16_CH1, FDCAN1_RX, USART3_TX, TIM15_BKIN, I2C1_SCL, EVENTOUT, USART6_TX, TIM4_CH3. Additional functions: none. [datasheet p.55]"
      },
      {
        "number": "33",
        "name": "VSS",
        "type": "power_in",
        "description": "Exposed pad, labelled VSS in the UFQFPN32 GP pinout (Figure 4) [datasheet p.37]; 3.50 x 3.50 mm typ (D2, E2 3.40-3.60 mm). [datasheet p.131]"
      }
    ],
    "provenance": {
      "datasheet": {
        "url": "https://www.st.com/resource/en/datasheet/stm32g0b1kb.pdf",
        "pages": 165,
        "sha256": "8433e47bc5da5cac459a1d3d5a6add183655061f5655d3c653248de65ca535c9",
        "source_tier": "mfr",
        "retrieved": "2026-10-27",
        "edition": "DS13560 Rev 6, February 2026"
      },
      "cad": "3D model Adom-generated with KiCad's package generator (kicad-footprint-generator package/no_lead) at ST DS13560 Rev 6 Table 83 UFQFPN32 values (tier 3; no redistributable ST or KiCad-library model fits), CC-BY-SA-4.0; footprint and symbol as used on Adom board designs",
      "pins": {
        "total": 33,
        "described": 33,
        "cites_pages": true,
        "refuses_to_fabricate": true
      },
      "build": {
        "tool": "board-derived part page builder 0.1: one-off Claude session scripts in Caleb Taylor's container (retired; not the Adom parts factory)",
        "pins": "KiCad symbol from the source board + adom-ds2sf datasheet extraction (claude-opus-4-7)",
        "at": "2026-10-16"
      }
    },
    "models_3d": [
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        "file": "stm32g0b1kbu6.step",
        "role": "plain",
        "up": "Z",
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        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "7ae4d90a64b22c011b9b2b25658a7d45899f4c08b3d76d262cd7eb702c6f38bb",
        "checked": "2026-10-27",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)",
        "source": {
          "manufacturer": "STMicroelectronics (drawing only)",
          "file": "stm32g0b1kbu6.step",
          "kind": "generated",
          "generator": "KiCad library 3D generator (kicad-footprint-generator 6ef68694, package/no_lead) at ST DS13560 Rev 6 Table 83 values",
          "source_page": "https://www.st.com/en/microcontrollers-microprocessors/stm32g0b1kb.html",
          "download": "none: ST CAD only via SamacSys / Ultra Librarian behind my.st.com login or e-mail validation (checked 2026-10-27/28)",
          "colour": "KiCad generator colours (black body, metal grey pins)",
          "retrieved": "2026-10-27",
          "posed_by": "generated in the footprint frame (identity); provenance/3d-model.json",
          "sha256": "7ae4d90a64b22c011b9b2b25658a7d45899f4c08b3d76d262cd7eb702c6f38bb"
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      {
        "file": "stm32g0b1kbu6-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
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        "sha256": "eefc133a0abc9d1da06cb2da0d77190b2f8036fa0381321917761e8a6dc9baf8",
        "checked": "2026-10-27",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "description": "STMicroelectronics Microcontrollers, UFQFPN-32(5x5). KiCad symbol, footprint and 3D as used on Adom boards; pin functions from the manufacturer datasheet."
}