component

STM32G0B1KBU6

Public Made by Adom

by adom

STMicroelectronics Microcontrollers, UFQFPN-32(5x5). KiCad symbol, footprint and 3D as used on Adom boards; pin functions from the manufacturer datasheet.

componentembedded processors & controllersstm32g0b1kbu6board-derived

Verified STM32G0B1KBU6

by Claude, at Caleb Taylor's request · last 28 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 6 records

28 Oct 2026Claude, at Caleb Taylor's requestValidated against ST's STM32G0B1xB/xC/xE datasheet DS13560 Rev 6 (February 2026)files match
SymbolFootprint3D modelPinsfor all variants
  • ✓Datasheet: replaced the LCSC copy (DS13560 Rev 3, January 2022) with ST's current DS13560 Rev 6, February 2026, from st.com
  • ✓Variant: STM32G0B1KBU6 = K 32 pins, B 128 KB, U UFQFPN, 6 = -40 to 85 C, no N option, so the GP pinout applies (ordering information p.161; N-suffix devices are the alternative pinout, p.11)
  • ✓All 33 pins match Figure 4 'STM32G0B1KxU UFQFPN32 pinout', GP version (p.37) and the LQFP32/UFQFPN32-GP column of Table 12 (p.47-55) by number and name, including PC14-OSC32_IN, PC15-OSC32_OUT, VDD/VDDA, VSS/VSSA, PF2-NRST, PA11 [PA9], PA12 [PA10], PA14-BOOT0; pin 33 is the exposed pad, labelled VSS in Figure 4. No renames needed
  • ✓Pin types agree with Table 12: the 30 port pins are I/O (bidirectional; PF2-NRST is RST/FT), VDD/VDDA and VSS/VSSA are supply (power_in); exposed pad 33 changed passive -> power_in (VSS ground)
  • ✓All 33 descriptions rewritten from Table 12 rows (I/O structure decoded with Table 11 p.46, alternate and additional functions, notes 1-6 on p.55), the power supply scheme (p.17) and Figure 4; citations re-pointed from Rev 3 to Rev 6 pages
  • •Footprint (designer custom STM_CDT UFQFPN-32-1EP 5x5) vs Figure 41/Table 83 (p.130-131) and Figure 42 footprint example (p.133): 32 pads 0.25 mm wide on e = 0.50 mm, as Figure 42; pads 0.875 mm long with centres at +/-2.4375 mm (span 2.00 to 2.875 mm from centre) vs Figure 42's 0.65 mm pads in a 5.50 mm outline (2.10 to 2.75 mm): longer by 0.10 mm inward and 0.125 mm outward, still covering the terminals (D/2 = 2.50, L 0.30-0.50, b 0.18-0.30) with 0.25 mm clearance to the exposed pad; exposed pad 3.50 x 3.50 mm = Figure 42 and D2/E2 typ (3.40-3.60), with four 1.41 mm paste windows; pin 1 at the top of the left column, numbering counter-clockwise as Figure 42
  • ✓3D model rebuilt (tier 3): the previous model was extracted from a board STEP with no licence. Tier 1 unusable (ST's CAD sits behind a my.st.com login/e-mail validation via SamacSys/Ultra Librarian, whose terms forbid library redistribution); tier 2 unusable (KiCad has no UFQFPN-32 EP3.5 model; QFN-32-1EP_5x5mm_P0.5mm_EP3.45x3.45mm is 0.77 mm tall vs A 0.50-0.60). Generated with kicad-footprint-generator @ 6ef68694 package/no_lead at DS13560 Table 83 values (patch in provenance/tools), CC-BY-SA-4.0
  • ✓3D body vs Figure 41/Table 83 (p.130-131): 5.00 x 5.00 x 0.55 mm (D = E 5.00 BSC, A 0.50-0.60); 32 terminals 0.40 x 0.25 mm at the edge on e = 0.50 (L 0.30-0.50, b 0.18-0.30), centres on the footprint pad centres; exposed pad 3.50 x 3.50 mm (D2/E2 3.40-3.60); pin-1 dimple top-left over pad 1 and bottom view pin 1 lower left as Figure 41 (docs/proof/stm32g0b1kbu6-3d-model.png)
  • ✓Pose: stm32g0b1kbu6.step and -etched.step Z-up, seated on z = 0, centred on the pad pattern (offset 0), footprint model binding identity (step_pose.py PASS); MPN etched on the top face with adom-chip-laser 0.2.0; GLBs from step2glb 0.13.2 (glTF-Transform, KHR_mesh_quantization) with PBR materials set by colour
  • •Not modelled: Figure 41's exposed-pad terminal-1 chamfer and corner radii (undimensioned, figure not to scale); terminal thickness A3 (not printed) left at the generator's 0.11 mm
  • ✓DigiKey 497-STM32G0B1KBU6-ND and Mouser 511-STM32G0B1KBU6 confirmed as STM32G0B1KBU6 by STMicroelectronics (2026-10-27)
  • ✓Symbol Datasheet / MPN / Manufacturer / DigiKey / Mouser / LCSC properties agree with page.json; footprint Datasheet property points at the manufacturer datasheet URL
  • ✓component-page-verify: all checks pass; adom-lbr validate OK
Evidencedatasheet (STMicroelectronics, DS13560 Rev 6)3D model views vs Figure 413D model provenance
Verified files✓ stm32g0b1kbu6.kicad_sym✓ stm32g0b1kbu6.kicad_mod✓ stm32g0b1kbu6.step
16 Oct 2026Claude (AI build)Datasheet pins not matched to a symbol pin: EPsuperseded
reviewfor all variants
  • •Datasheet pins not matched to a symbol pin: EP
16 Oct 2026Claude (AI build)3D model provenance: extracted from the source board STEP export (designer custom library ...superseded
reviewfor all variants
  • •3D model provenance: extracted from the source board STEP export (designer custom library STM_CDT); the upstream model licence is not stated, so the page licence is NOASSERTION.
16 Oct 2026Claude (AI build)Footprint is the designer custom STM_CDT:STM32G0B1_UFQFPN-32-1EP_5x5mm_P0.5mm_EP3.5x3.5mm;...superseded
reviewfor all variants
  • •Footprint is the designer custom STM_CDT:STM32G0B1_UFQFPN-32-1EP_5x5mm_P0.5mm_EP3.5x3.5mm; check it against the UFQFPN32 package drawing.
16 Oct 2026Claude (AI build)Symbol pin names changed to the datasheet spelling (Figure 12, GP version): PC14-OSC32_IN,...superseded
reviewfor all variants
  • •Symbol pin names changed to the datasheet spelling (Figure 12, GP version): PC14-OSC32_IN, PC15-OSC32_OUT, VDD/VDDA, VSS/VSSA, PF2-NRST, PA9, PA10, PA11 [PA9], PA12 [PA10], PA14-BOOT0.
16 Oct 2026Claude (AI build)Automated build checks (awaiting human validation)superseded
SymbolFootprint3D modelPinsfor all variants
  • ✓Footprint extracted pad-for-pad from the source board and normalized to the footprint frame (back-side parts un-mirrored)
  • ✓3D model seated z=0 at footprint origin (placement inverse; method centroid-matched to KiCad library models on 59 cases)
  • ✓adom-lbr generate + lint passed
  • ✓33 of 33 pins described from the datasheet (adom-ds2sf, page-cited)
  • •Not yet checked by a person: land pattern vs datasheet, pin-1/orientation, 3D body vs drawing
Evidencedatasheet
Verified files! stm32g0b1kbu6.kicad_sym✓ stm32g0b1kbu6.kicad_mod! stm32g0b1kbu6.step
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Generated by board-derived · KiCad file format 20241209
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docs Publish 0.1.1 · Caleb 1d ago
provenance Publish 0.1.1 · Caleb 1d ago
package.json Publish 0.1.2 · Caleb 22h ago
page.json Set visibility: public · Caleb 22h ago
README.md Publish 0.1.1 · Caleb 1d ago
stm32g0b1kbu6-etched.glb Publish 0.1.1 · Caleb 1d ago
stm32g0b1kbu6-etched.step Publish 0.1.1 · Caleb 1d ago
stm32g0b1kbu6-hero.glb Publish 0.1.1 · Caleb 1d ago
stm32g0b1kbu6-hero.overlay.json Publish 0.1.1 · Caleb 1d ago
stm32g0b1kbu6.glb Publish 0.1.1 · Caleb 1d ago
stm32g0b1kbu6.kicad_mod Add component CAD, datasheet and docs (1) · Caleb 12d ago
stm32g0b1kbu6.kicad_sym Publish 0.1.2 · Caleb 22h ago
stm32g0b1kbu6.lbr Publish 0.1.1 · Caleb 1d ago
stm32g0b1kbu6.step Publish 0.1.1 · Caleb 1d ago
verification.json Publish 0.1.2 · Caleb 22h ago

STM32G0B1KBU6

STMicroelectronics · Microcontrollers · UFQFPN-32(5x5)

STM32G0B1KBU6 from STMicroelectronics, in a UFQFPN-32(5x5). Symbol and footprint are the ones used on Adom board designs; the 3D model is generated with KiCad's package generator at the datasheet's UFQFPN32 dimensions (DS13560 Table 83), seated in the footprint frame. Pin functions are extracted from the manufacturer datasheet with page references.

Pinout

Pin Name Type Function
1 PB9 bidirectional Port I/O PB9, I/O structure FT_f: 5 V tolerant, Fm+ capable [datasheet p.46]. Alternate functions: IR_OUT, UCPD2_FRSTX, TIM17_CH1, FDCAN1_TX, USART3_RX, SPI2_NSS/I2S2_WS, I2C1_SDA, EVENTOUT, USART6_RX, TIM4_CH4. Additional functions: none. [datasheet p.55]
2 PC14-OSC32_IN bidirectional Port I/O PC14-OSC32_IN, I/O structure FT: 5 V tolerant [datasheet p.46]. Alternate functions: TIM1_BKIN2. Additional functions: OSC32_IN, OSC_IN. [datasheet p.47] Supplied through the power switch (3 mA): as an output it is limited to 2 MHz with 30 pF and can sink but not source current; after an RTC domain power-up it operates as a GPIO whose function then depends on the RTC registers, which system reset does not reset (Table 12 notes 1-2). [datasheet p.55]
3 PC15-OSC32_OUT bidirectional Port I/O PC15-OSC32_OUT, I/O structure FT: 5 V tolerant [datasheet p.46]. Alternate functions: OSC32_EN, OSC_EN, TIM15_BKIN. Additional functions: OSC32_OUT. [datasheet p.47] Supplied through the power switch (3 mA): as an output it is limited to 2 MHz with 30 pF and can sink but not source current; after an RTC domain power-up it operates as a GPIO whose function then depends on the RTC registers, which system reset does not reset (Table 12 notes 1-2). [datasheet p.55]
4 VDD/VDDA power_in Supply pin (S) [datasheet p.47]. VDD 1.7 V to 3.6 V: external supply for the internal regulator, system analog and the I/Os (VDDIO1 = VDD); the same pin provides VDDA, the analog supply for the ADC, DAC, voltage reference buffer and comparators. On packages without the pin, VBAT is bonded to VDD/VDDA and VREF+ is connected to VDD (keep the voltage reference buffer disabled). [datasheet p.17]
5 VSS/VSSA power_in Supply pin (S): ground, VSS and VSSA on one pin. [datasheet p.47]
6 PF2-NRST bidirectional Port I/O PF2-NRST, I/O structure RST, FT: reset pin with embedded weak pull-up resistor; 5 V tolerant when used as GPIO [datasheet p.46]. Alternate functions: MCO, LPUART2_TX, LPUART2_RTS_DE. Additional functions: NRST. [datasheet p.48] RST I/O structure when configured as reset, FT when configured as GPIO (Table 12 note 3). [datasheet p.55]
7 PA0 bidirectional Port I/O PA0, I/O structure FT_a: 5 V tolerant, analog switch function [datasheet p.46]. Alternate functions: SPI2_SCK/I2S2_CK, USART2_CTS, TIM2_CH1_ETR, USART4_TX, LPTIM1_OUT, UCPD2_FRSTX, COMP1_OUT. Additional functions: COMP1_INM8, ADC_IN0, TAMP_IN2, WKUP1. [datasheet p.48]
8 PA1 bidirectional Port I/O PA1, I/O structure FT_ea: 5 V tolerant, switchable diode to VDDIOx, analog switch function [datasheet p.46]. Alternate functions: SPI1_SCK/I2S1_CK, USART2_RTS_DE_CK, TIM2_CH2, USART4_RX, TIM15_CH1N, I2C1_SMBA, EVENTOUT. Additional functions: COMP1_INP2, ADC_IN1. [datasheet p.48]
9 PA2 bidirectional Port I/O PA2, I/O structure FT_a: 5 V tolerant, analog switch function [datasheet p.46]. Alternate functions: SPI1_MOSI/I2S1_SD, USART2_TX, TIM2_CH3, UCPD1_FRSTX, TIM15_CH1, LPUART1_TX, COMP2_OUT. Additional functions: COMP2_INM8, ADC_IN2, WKUP4, LSCO. [datasheet p.48]
10 PA3 bidirectional Port I/O PA3, I/O structure FT_ea: 5 V tolerant, switchable diode to VDDIOx, analog switch function [datasheet p.46]. Alternate functions: SPI2_MISO/I2S2_MCK, USART2_RX, TIM2_CH4, UCPD2_FRSTX, TIM15_CH2, LPUART1_RX, EVENTOUT. Additional functions: COMP2_INP2, ADC_IN3. [datasheet p.49]
11 PA4 bidirectional Port I/O PA4, I/O structure TT_a: 3.6 V tolerant, analog switch function [datasheet p.46]. Alternate functions: SPI1_NSS/I2S1_WS, SPI2_MOSI/I2S2_SD, USART6_TX, TIM14_CH1, LPTIM2_OUT, UCPD2_FRSTX, EVENTOUT, SPI3_NSS. Additional functions: ADC_IN4, DAC1_OUT1, TAMP_IN1, RTC_TS, RTC_OUT1, WKUP2. [datasheet p.49]
12 PA5 bidirectional Port I/O PA5, I/O structure TT_ea: 3.6 V tolerant, switchable diode to VDDIOx, analog switch function [datasheet p.46]. Alternate functions: SPI1_SCK/I2S1_CK, CEC, TIM2_CH1_ETR, USART6_RX, USART3_TX, LPTIM2_ETR, UCPD1_FRSTX, EVENTOUT. Additional functions: ADC_IN5, DAC1_OUT2. [datasheet p.49]
13 PA6 bidirectional Port I/O PA6, I/O structure FT_ea: 5 V tolerant, switchable diode to VDDIOx, analog switch function [datasheet p.46]. Alternate functions: SPI1_MISO/I2S1_MCK, TIM3_CH1, TIM1_BKIN, USART6_CTS, USART3_CTS, TIM16_CH1, LPUART1_CTS, COMP1_OUT, I2C2_SDA, I2C3_SDA. Additional functions: ADC_IN6. [datasheet p.49]
14 PA7 bidirectional Port I/O PA7, I/O structure FT_a: 5 V tolerant, analog switch function [datasheet p.46]. Alternate functions: SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM1_CH1N, USART6_RTS_DE_CK, TIM14_CH1, TIM17_CH1, UCPD1_FRSTX, COMP2_OUT, I2C2_SCL, I2C3_SCL. Additional functions: ADC_IN7. [datasheet p.49]
15 PB0 bidirectional Port I/O PB0, I/O structure FT_ea: 5 V tolerant, switchable diode to VDDIOx, analog switch function [datasheet p.46]. Alternate functions: SPI1_NSS/I2S1_WS, TIM3_CH3, TIM1_CH2N, FDCAN2_RX, USART3_RX, LPTIM1_OUT, UCPD1_FRSTX, COMP1_OUT, USART5_TX, LPUART2_CTS. Additional functions: COMP3_INP0, ADC_IN8. [datasheet p.50]
16 PB1 bidirectional Port I/O PB1, I/O structure FT_ea: 5 V tolerant, switchable diode to VDDIOx, analog switch function [datasheet p.46]. Alternate functions: TIM14_CH1, TIM3_CH4, TIM1_CH3N, FDCAN2_TX, USART3_RTS_DE_CK, LPTIM2_IN1, LPUART1_RTS_DE, COMP3_OUT, USART5_RX, LPUART2_RTS_DE. Additional functions: COMP1_INM6, ADC_IN9. [datasheet p.50]
17 PB2 bidirectional Port I/O PB2, I/O structure FT_ea: 5 V tolerant, switchable diode to VDDIOx, analog switch function [datasheet p.46]. Alternate functions: SPI2_MISO/I2S2_MCK, MCO2, USART3_TX, LPTIM1_OUT, EVENTOUT. Additional functions: COMP1_INP1, COMP3_INM6, ADC_IN10. [datasheet p.50]
18 PA8 bidirectional Port I/O PA8, I/O structure FT_fcs: 5 V tolerant, Fm+ capable, USB Type-C PD capable, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: MCO, SPI2_NSS/I2S2_WS, TIM1_CH1, CRS1_SYNC, LPTIM2_OUT, EVENTOUT, I2C2_SMBA. Additional functions: UCPD1_CC1. [datasheet p.51] Table 12 note 4: upon reset a pull-down might be present on PA8, PB15, PD0 or PD2 depending on the voltage on PA9, PA10, PD1 and PD3 respectively; strobe the UCPDx_STROBE bits in SYSCFG_CFGR1 at start-up to disable it. [datasheet p.55]
19 PA9 bidirectional Port I/O PA9, I/O structure FT_fds: 5 V tolerant, Fm+ capable, USB Type-C PD Dead Battery function, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: MCO, USART1_TX, TIM1_CH2, SPI2_MISO/I2S2_MCK, TIM15_BKIN, I2C1_SCL, EVENTOUT, I2C2_SCL. Additional functions: UCPD1_DBCC1. [datasheet p.51] Table 12 note 4: upon reset a pull-down might be present on PA8, PB15, PD0 or PD2 depending on the voltage on PA9, PA10, PD1 and PD3 respectively; strobe the UCPDx_STROBE bits in SYSCFG_CFGR1 at start-up to disable it. [datasheet p.55]
20 PC6 bidirectional Port I/O PC6, I/O structure FT_s: 5 V tolerant, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: UCPD1_FRSTX, TIM3_CH1, TIM2_CH3, LPUART2_TX. Additional functions: none. [datasheet p.51]
21 PA10 bidirectional Port I/O PA10, I/O structure FT_fds: 5 V tolerant, Fm+ capable, USB Type-C PD Dead Battery function, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: SPI2_MOSI/I2S2_SD, USART1_RX, TIM1_CH3, MCO2, TIM17_BKIN, I2C1_SDA, EVENTOUT, I2C2_SDA. Additional functions: UCPD1_DBCC2. [datasheet p.52] Table 12 note 4: upon reset a pull-down might be present on PA8, PB15, PD0 or PD2 depending on the voltage on PA9, PA10, PD1 and PD3 respectively; strobe the UCPDx_STROBE bits in SYSCFG_CFGR1 at start-up to disable it. [datasheet p.55]
22 PA11 [PA9] bidirectional Port I/O PA11 [PA9], I/O structure FT_fus: 5 V tolerant, Fm+ capable, USB function, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: SPI1_MISO/I2S1_MCK, USART1_CTS, TIM1_CH4, FDCAN1_RX, TIM1_BKIN2, I2C2_SCL, COMP1_OUT. Additional functions: USB_DM. [datasheet p.52] PA9/PA10 can be remapped in place of PA11/PA12 (default mapping) using SYSCFG_CFGR1 (Table 12 note 5). [datasheet p.55]
23 PA12 [PA10] bidirectional Port I/O PA12 [PA10], I/O structure FT_fus: 5 V tolerant, Fm+ capable, USB function, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: SPI1_MOSI/I2S1_SD, USART1_RTS_DE_CK, TIM1_ETR, FDCAN1_TX, I2S_CKIN, I2C2_SDA, COMP2_OUT. Additional functions: USB_DP. [datasheet p.52] PA9/PA10 can be remapped in place of PA11/PA12 (default mapping) using SYSCFG_CFGR1 (Table 12 note 5). [datasheet p.55]
24 PA13 bidirectional Port I/O PA13, I/O structure FT_es: 5 V tolerant, switchable diode to VDDIOx, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: SWDIO, IR_OUT, USB_NOE, EVENTOUT, LPUART2_RX. Additional functions: none. [datasheet p.53] Upon reset configured as SW debug alternate function, with the internal pull-up on PA13 and pull-down on PA14 active (Table 12 note 6). [datasheet p.55]
25 PA14-BOOT0 bidirectional Port I/O PA14-BOOT0, I/O structure FT_s: 5 V tolerant, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: SWCLK, USART2_TX, EVENTOUT, LPUART2_TX. Additional functions: BOOT0. [datasheet p.53] Upon reset configured as SW debug alternate function, with the internal pull-up on PA13 and pull-down on PA14 active (Table 12 note 6). [datasheet p.55]
26 PA15 bidirectional Port I/O PA15, I/O structure FT_s: 5 V tolerant, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: SPI1_NSS/I2S1_WS, USART2_RX, TIM2_CH1_ETR, MCO2, USART4_RTS_DE_CK, USART3_RTS_DE_CK, USB_NOE, EVENTOUT, I2C2_SMBA, SPI3_NSS. Additional functions: none. [datasheet p.53]
27 PB3 bidirectional Port I/O PB3, I/O structure FT_a: 5 V tolerant, analog switch function [datasheet p.46]. Alternate functions: SPI1_SCK/I2S1_CK, TIM1_CH2, TIM2_CH2, USART5_TX, USART1_RTS_DE_CK, I2C3_SCL, EVENTOUT, I2C2_SCL, SPI3_SCK. Additional functions: COMP2_INM6. [datasheet p.54]
28 PB4 bidirectional Port I/O PB4, I/O structure FT_a: 5 V tolerant, analog switch function [datasheet p.46]. Alternate functions: SPI1_MISO/I2S1_MCK, TIM3_CH1, USART5_RX, USART1_CTS, TIM17_BKIN, I2C3_SDA, EVENTOUT, I2C2_SDA, SPI3_MISO. Additional functions: COMP2_INP0. [datasheet p.54]
29 PB5 bidirectional Port I/O PB5, I/O structure FT: 5 V tolerant [datasheet p.46]. Alternate functions: SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM16_BKIN, FDCAN2_RX, LPTIM1_IN1, I2C1_SMBA, COMP2_OUT, USART5_RTS_DE_CK, SPI3_MOSI. Additional functions: WKUP6. [datasheet p.54]
30 PB6 bidirectional Port I/O PB6, I/O structure FT_fa: 5 V tolerant, Fm+ capable, analog switch function [datasheet p.46]. Alternate functions: USART1_TX, TIM1_CH3, TIM16_CH1N, FDCAN2_TX, SPI2_MISO/I2S2_MCK, LPTIM1_ETR, I2C1_SCL, EVENTOUT, USART5_CTS, TIM4_CH1, LPUART2_TX. Additional functions: COMP2_INP1. [datasheet p.55]
31 PB7 bidirectional Port I/O PB7, I/O structure FT_fa: 5 V tolerant, Fm+ capable, analog switch function [datasheet p.46]. Alternate functions: USART1_RX, SPI2_MOSI/I2S2_SD, TIM17_CH1N, USART4_CTS, LPTIM1_IN2, I2C1_SDA, EVENTOUT, TIM4_CH2, LPUART2_RX. Additional functions: COMP2_INM7, PVD_IN. [datasheet p.55]
32 PB8 bidirectional Port I/O PB8, I/O structure FT_f: 5 V tolerant, Fm+ capable [datasheet p.46]. Alternate functions: CEC, SPI2_SCK/I2S2_CK, TIM16_CH1, FDCAN1_RX, USART3_TX, TIM15_BKIN, I2C1_SCL, EVENTOUT, USART6_TX, TIM4_CH3. Additional functions: none. [datasheet p.55]
33 VSS power_in Exposed pad, labelled VSS in the UFQFPN32 GP pinout (Figure 4) [datasheet p.37]; 3.50 x 3.50 mm typ (D2, E2 3.40-3.60 mm). [datasheet p.131]

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package UFQFPN-32(5x5)
Category Embedded Processors & Controllers
Pins 33
LCSC C5159549
Mouser 511-STM32G0B1KBU6
DigiKey 497-STM32G0B1KBU6-ND
Distributor summary (LCSC listing, not datasheet) -40℃+85℃ 1.7V3.6V 128KB 144KB 30 32 Bit 64MHz ARM Cortex-M0+ Built-in+External FLASH UFQFPN-32(5x5) Microcontrollers (MCU/MPU/SOC) ROHS

CAD

  • Symbol: stm32g0b1kbu6 (source library MCU_ST_STM32G0:STM32G0B1KBUx)
  • Footprint: STM_CDT:STM32G0B1_UFQFPN-32-1EP_5x5mm_P0.5mm_EP3.5x3.5mm
  • 3D model path in footprint: ${KIPRJMOD}/stm32g0b1kbu6.step
  • 3D files: stm32g0b1kbu6-etched.step / stm32g0b1kbu6-etched.glb carry the MPN etch as a separate Adom.LaserEtch part; stm32g0b1kbu6.step / stm32g0b1kbu6.glb are the bare model. The model is AI-generated (Claude, for Adom) with KiCad's package generator at ST DS13560 Rev 6 Table 83 values (5.00 x 5.00 x 0.55 mm, EP 3.50 x 3.50 mm, L 0.40, b 0.25); it is not ST's CAD and the etched MPN is a virtual mark. Build recipe and source record: provenance/3d-model.json, provenance/tools/; views against Figure 41: docs/proof/stm32g0b1kbu6-3d-model.png.
  • EAGLE/Fusion library: stm32g0b1kbu6.lbr (adom-lbr)

Provenance

  • Datasheet: STMicroelectronics STM32G0B1xB/xC/xE datasheet (DS13560) (DS13560 Rev 6, February 2026, sha256 8433e47bc5da5cac, retrieved 2026-10-27, tier: mfr)
  • CAD: Footprint and symbol as used on Adom board designs; 3D model Adom-generated with the KiCad generator from ST DS13560 Rev 6 Table 83 (p.131).
  • License: CC-BY-SA-4.0 (Adom content, including the 3D model).
  • Pins: KiCad symbol from the source board + adom-ds2sf datasheet extraction (claude-opus-4-7).

Datasheet PDF