component

STM32F103C8T6 - Arm Cortex-M3 MCU (Blue Pill)

Public Made by Adom

by adom

STMicroelectronics mainstream Arm Cortex-M3 MCU. 72 MHz, 64 KB Flash, 20 KB SRAM, USB, CAN, LQFP-48. The workhorse Blue Pill microcontroller.

componentmicrocontrollermcuarmcortex-m3stm32stmicroelectronicslqfp-48blue-pill
Overview Files Skills Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
Propose a change
Name Last commit message Last updated
docs Publish 0.2.0 3d ago
keypages keypages: 5 curated datasheet pages for the readme quick-look strip 4d ago
screenshots Publish 0.1.0 5d ago
skills Publish 0.2.2 3d ago
viewers 3d viewer: smooth lift, lower lift height (stays framed), slower reflow/power-on pulses, demo pacing 3d ago
board-3d.html clean Overview: interactive symbol|footprint|board-context-3D + ds2sf pin map + specs/sourcing/provenance 4d ago
footprint.html clean Overview: interactive symbol|footprint|board-context-3D + ds2sf pin map + specs/sourcing/provenance 4d ago
package.json Publish 0.2.2 3d ago
page.json Publish 0.2.2 3d ago
readme.html readme: cache-bust viewer iframes per build 4d ago
README.md datasheet: compact page-picker (thumbnails + click-to-enlarge lightbox) replaces stacked figures; full-PDF link restored 4d ago
stm32f103c8-datasheet.pdf add full 116-page datasheet PDF for in-viewer reading 4d ago
stm32f103c8t6-board.glb 3D fix: preserve chip metallic leads (merge path, not flat rebuild) + make laser etch subtle (one line, small); keep pick-and-place animation 23h ago
stm32f103c8t6.glb 3D fix: preserve chip metallic leads (merge path, not flat rebuild) + make laser etch subtle (one line, small); keep pick-and-place animation 23h ago
STM32F103C8T6.kicad_mod Publish 0.2.0 3d ago
stm32f103c8t6.step 3D fix: preserve chip metallic leads (merge path, not flat rebuild) + make laser etch subtle (one line, small); keep pick-and-place animation 23h ago
STM32F103C8Tx.kicad_sym Publish 0.1.0 5d ago
symbol.html clean Overview: interactive symbol|footprint|board-context-3D + ds2sf pin map + specs/sourcing/provenance 4d ago

STM32F103C8T6

STMicroelectronics mainstream Arm Cortex-M3 microcontroller. 72 MHz, 64 KB Flash, 20 KB SRAM, LQFP-48. The workhorse "Blue Pill" MCU.

The interactive symbol, footprint, and 3D model above are rendered by the wiki from the KiCad official CAD shipped with this page. Pin 1 is the square pad, top-left (IPC-7351).

Specifications

Spec Value
Core ARM Cortex-M3
Max frequency 72 MHz
Flash 64 KB
RAM 20 KB
GPIO 37
Supply (min) 2 V
Supply (max) 3.6 V

Peripherals: TIM x4 (16-bit), ADC x2 (12-bit), USART, SPI, I2C, CAN, USB 2.0 FS

Source: ST product catalog (mcu_families seed, manufacturer XLSX import).

Pin configuration

48 pins, extracted from the ST datasheet by ds2sf with per-pin function descriptions. Muxed protocol-select pins (5, 6, 10, 20, 32, 33) are flagged for review, not silently resolved.

Pin Name Group Function (from datasheet)
1 VBAT POWER Backup battery supply for RTC and backup registers. Typical operating range 1.8 to 3.6 V. Supplies the RTC and backup domain when VDD is off.
2 PC13-TAMPER-RTC GPIO GPIO port C bit 13, muxed with TAMPER input and RTC output. Supplied through the backup power switch (limited to 3 mA sink); output speed limited to 2 MHz with max 30 pF load; must not source current.
3 PC14-OSC32_IN TIMING GPIO port C bit 14, muxed with 32 kHz LSE oscillator input (OSC32_IN). Backup-domain pin routed through the power switch; same 2 MHz / 30 pF drive limitation as PC13.
4 PC15-OSC32_OUT TIMING GPIO port C bit 15, muxed with 32 kHz LSE oscillator output (OSC32_OUT). Backup-domain pin routed through the power switch; same 2 MHz / 30 pF drive limitation as PC13/PC14.
5 PD0-OSC_IN TIMING HSE crystal oscillator input (OSC_IN) after reset; remappable to GPIO PD0 by software. In GPIO mode limited to 50 MHz output. Connect to 4-16 MHz crystal or external clock.
6 PD1-OSC_OUT TIMING HSE crystal oscillator output (OSC_OUT) after reset; remappable to GPIO PD1 by software. In GPIO mode limited to 50 MHz output.
7 NRST CONTROL Active-low bidirectional device reset. Pulled low by internal or external reset sources; external pull-up recommended (typ 40 kΩ internal weak pull-up).
8 VSSA POWER Analog ground reference for ADC, reset block, PLL, and analog peripherals. Connect to digital ground at a single point.
9 VDDA POWER Analog supply for ADC, reset block, PLL, and analog I/O. 2.0 to 3.6 V. Decouple with 1 µF + 10 nF close to the pin.
10 PA0-WKUP GPIO GPIO port A bit 0, 5 V-tolerant when configured as digital input. Alternate functions: standby WKUP, USART2_CTS (remap), ADC12_IN0, TIM2_CH1_ETR.
11 PA1 GPIO GPIO port A bit 1. Alternate functions: USART2_RTS, ADC12_IN1, TIM2_CH2.
12 PA2 GPIO GPIO port A bit 2. Alternate functions: USART2_TX, ADC12_IN2, TIM2_CH3.
13 PA3 GPIO GPIO port A bit 3. Alternate functions: USART2_RX, ADC12_IN3, TIM2_CH4.
14 PA4 GPIO GPIO port A bit 4. Alternate functions: SPI1_NSS, USART2_CK, ADC12_IN4.
15 PA5 GPIO GPIO port A bit 5. Alternate functions: SPI1_SCK, ADC12_IN5.
16 PA6 GPIO GPIO port A bit 6. Alternate functions: SPI1_MISO, ADC12_IN6, TIM3_CH1; remap: TIM1_BKIN.
17 PA7 GPIO GPIO port A bit 7. Alternate functions: SPI1_MOSI, ADC12_IN7, TIM3_CH2; remap: TIM1_CH1N.
18 PB0 GPIO GPIO port B bit 0. Alternate functions: ADC12_IN8, TIM3_CH3; remap: TIM1_CH2N.
19 PB1 GPIO GPIO port B bit 1. Alternate functions: ADC12_IN9, TIM3_CH4; remap: TIM1_CH3N.
20 PB2 GPIO GPIO port B bit 2, 5 V-tolerant. Doubles as BOOT1 boot mode selection input sampled at reset.
21 PB10 GPIO GPIO port B bit 10, 5 V-tolerant. Alternate functions: I2C2_SCL, USART3_TX; remap: TIM2_CH3.
22 PB11 GPIO GPIO port B bit 11, 5 V-tolerant. Alternate functions: I2C2_SDA, USART3_RX; remap: TIM2_CH4.
23 VSS_1 POWER Digital ground, group 1. Connect to the ground plane; keep short return path to VDD_1 decoupling.
24 VDD_1 POWER Digital supply, group 1. 2.0 to 3.6 V. Decouple with 100 nF close to the pin.
25 PB12 GPIO GPIO port B bit 12, 5 V-tolerant. Alternate functions: SPI2_NSS, I2C2_SMBAl, USART3_CK, TIM1_BKIN.
26 PB13 GPIO GPIO port B bit 13, 5 V-tolerant. Alternate functions: SPI2_SCK, USART3_CTS, TIM1_CH1N.
27 PB14 GPIO GPIO port B bit 14, 5 V-tolerant. Alternate functions: SPI2_MISO, USART3_RTS, TIM1_CH2N.
28 PB15 GPIO GPIO port B bit 15, 5 V-tolerant. Alternate functions: SPI2_MOSI, TIM1_CH3N.
29 PA8 GPIO GPIO port A bit 8, 5 V-tolerant. Alternate functions: USART1_CK, TIM1_CH1, MCO (master clock output).
30 PA9 GPIO GPIO port A bit 9, 5 V-tolerant. Alternate functions: USART1_TX, TIM1_CH2.
31 PA10 GPIO GPIO port A bit 10, 5 V-tolerant. Alternate functions: USART1_RX, TIM1_CH3.
32 PA11 USB GPIO port A bit 11, 5 V-tolerant. Alternate functions: USART1_CTS, CANRX, USBDM (USB D-), TIM1_CH4.
33 PA12 USB GPIO port A bit 12, 5 V-tolerant. Alternate functions: USART1_RTS, CANTX, USBDP (USB D+), TIM1_ETR.
34 PA13 DEBUG GPIO port A bit 13, 5 V-tolerant. Default after reset: JTMS/SWDIO (serial-wire debug data/JTAG mode select). Can be released to GPIO via SWJ-DP disable.
35 VSS_2 POWER Digital ground, group 2. Connect to the ground plane; pair with VDD_2 decoupling.
36 VDD_2 POWER Digital supply, group 2. 2.0 to 3.6 V. Decouple with 100 nF close to the pin.
37 PA14 DEBUG GPIO port A bit 14, 5 V-tolerant. Default after reset: JTCK/SWCLK (serial-wire debug clock/JTAG clock).
38 PA15 DEBUG GPIO port A bit 15, 5 V-tolerant. Default after reset: JTDI (JTAG data in). Remappable to TIM2_CH1_ETR/PA15/SPI1_NSS.
39 PB3 DEBUG GPIO port B bit 3, 5 V-tolerant. Default after reset: JTDO / TRACESWO. Remappable to TIM2_CH2, PB3, SPI1_SCK.
40 PB4 DEBUG GPIO port B bit 4, 5 V-tolerant. Default after reset: NJTRST (JTAG reset, active low). Remappable to TIM3_CH1, PB4, SPI1_MISO.
41 PB5 GPIO GPIO port B bit 5 (NOT 5 V-tolerant on this pin). Alternate functions: I2C1_SMBAl; remap: TIM3_CH2, SPI1_MOSI.
42 PB6 GPIO GPIO port B bit 6, 5 V-tolerant. Alternate functions: I2C1_SCL, TIM4_CH1; remap: USART1_TX.
43 PB7 GPIO GPIO port B bit 7, 5 V-tolerant. Alternate functions: I2C1_SDA, TIM4_CH2; remap: USART1_RX.
44 BOOT0 CONTROL Boot mode selection input sampled at reset (with BOOT1/PB2): selects boot from Flash, System memory (bootloader), or embedded SRAM. Must be tied to a defined logic level.
45 PB8 GPIO GPIO port B bit 8, 5 V-tolerant. Alternate functions: TIM4_CH3; remap: I2C1_SCL, CANRX.
46 PB9 GPIO GPIO port B bit 9, 5 V-tolerant. Alternate functions: TIM4_CH4; remap: I2C1_SDA, CANTX.
47 VSS_3 POWER Digital ground, group 3. Connect to the ground plane; pair with VDD_3 decoupling.
48 VDD_3 POWER Digital supply, group 3. 2.0 to 3.6 V. Decouple with 100 nF close to the pin.

Sourcing

Distributor Part number Stock (2026-07-15)
DigiKey 497-6063-ND 804
LCSC C8734 218,502

Provenance

  • Pin functions and pinout: ds2sf extraction of the ST datasheet (116 pages, sha256 0596dd57693c93d2, source lcsc). Claude reads the PDF, cites pages, and refuses to fabricate.
  • Specs: ST product catalog.
  • Footprint, 3D, symbol: KiCad official libraries (CC-BY-SA 4.0 with exception). Symbol is MCU_ST_STM32F1:STM32F103C8Tx, extends-merged so the viewer resolves geometry.
  • Datasheet: ST STM32F103x8/xB.