# STD65N55F3

**STMicroelectronics** · MOSFETs · DPAK

STD65N55F3 from STMicroelectronics, in a DPAK. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | G | input | Gate terminal of the N-channel MOSFET, with gate-source voltage VGS rated at ±20 V in the absolute maximum ratings. |
| 2 | D | passive | Drain terminal, electrically connected to the TAB, with drain-source voltage VDS rated at 55 V in the absolute maximum ratings. |
| 3 | S | passive | Source terminal of the N-channel MOSFET; the datasheet rates source-drain current ISD at 80 A continuous and 320 A pulsed. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | DPAK |
| Category | Transistors/Thyristors |
| Pins | 3 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-source voltage | VDS |  |  | 55 | V |  | 2 |
| Gate-source voltage | VGS | -20 |  | 20 | V |  | 2 |
| Drain current (continuous) | ID |  |  | 80 | A | TC = 25 °C | 2 |
| Drain current (continuous) | ID |  |  | 56 | A | TC = 100 °C | 2 |
| Drain current (pulsed) | IDM |  |  | 320 | A | Pulse width limited by safe operating area | 2 |
| Total power dissipation | PTOT |  |  | 110 | W | TC = 25 °C | 2 |
| Peak diode recovery | dv/dt |  |  | 11 | V/ns | ISD ≤ 65A, di/dt ≤ 300 A/μs, VDD ≤ V(BR)DSS, Tj ≤ Tjmax | 2 |
| Single pulse avalanche energy | EAS |  |  | 390 | mJ | Starting Tj = 25°C, ID = 32 A, VDD = 25 V | 2 |
| Operating junction temperature range | Tj | -55 |  | 175 | °C |  | 2 |
| Thermal resistance junction-case | Rthj-case |  | 1.36 |  | °C/W |  | 2 |
| Thermal resistance junction-pcb | Rthj-pcb |  | 50 |  | °C/W | Mounted on an 1- inch² FR-4 board, 2oz Cu | 2 |
| Drain-source breakdown voltage | V(BR)DSS | 55 |  |  | V | VGS = 0 V, ID = 250 µA | 3 |
| Zero gate voltage drain current | IDSS |  |  | 10 | µA | VGS = 0 V, VDS = 55 V | 3 |
| Zero gate voltage drain current | IDSS |  |  | 100 | µA | VGS = 0 V, VDS = 55 V, TC = 125 °C | 3 |
| Gate-body leakage current | IGSS | -200 |  | 200 | nA | VGS = ±20 V, VDS = 0 V | 3 |
| Gate threshold voltage | VGS(th) | 2 |  | 4 | V | VDS = VGS, ID = 250 µA | 3 |
| Static drain-source on-resistance | RDS(on) |  | 6.5 | 8.5 | mΩ | VGS = 10 V, ID = 32 A | 3 |
| Total gate charge | Qg |  | 33.5 | 45 | nC | VDD = 27 V, ID = 65 A, VGS = 0 to 10 V | 3 |
| Source-drain current | ISD |  |  | 80 | A |  | 4 |
| Source-drain current (pulsed) | ISDM |  |  | 320 | A | Pulsed: pulse duration = 300 μs, duty cycle 1.5% | 4 |

## CAD (KiCad official)

- Symbol: `STD65N55F3`
- Footprint: `Package_TO_SOT_SMD:TO-252-2`
- 3D model: DPAK (KiCad packages3D, STEP)
- 3D model files: `std65n55f3-etched.step` / `std65n55f3-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `std65n55f3.step` / `std65n55f3.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [STMicroelectronics datasheet](https://www.st.com/resource/en/datasheet/std65n55f3.pdf) (17 pp, sha256 `4d52fdbad0cfe733`, retrieved 2026-10-11, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/std65n55f3-datasheet.pdf)