SN65MLVD206DR

{
  "schema_version": 1,
  "type": "component",
  "slug": "sn65mlvd206dr",
  "title": "SN65MLVD206DR",
  "brief": "Texas Instruments LVDS ICs, SOIC-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "interface",
    "sn65mlvd206dr"
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  "component": {
    "mpn": "SN65MLVD206DR",
    "manufacturer": "Texas Instruments",
    "package": "SOIC-8",
    "pin_count": 8,
    "category": "Interface",
    "subcategory": "LVDS ICs",
    "datasheet": "https://www.ti.com/lit/ds/symlink/sn65mlvd206.pdf",
    "parts": {
      "symbol": "sn65mlvd206dr.kicad_sym",
      "footprint": "sn65mlvd206dr.kicad_mod",
      "model_3d": "sn65mlvd206dr-etched.glb",
      "model_3d_plain": "sn65mlvd206dr.glb",
      "model_3d_step": "sn65mlvd206dr-etched.step",
      "model_3d_step_plain": "sn65mlvd206dr.step",
      "lbr": "sn65mlvd206dr.lbr"
    },
    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "R",
        "type": "output",
        "description": "Receiver single-ended CMOS output (LVTTL). Drives VOH ≥ 2.4 V at IOH = -8 mA and VOL ≤ 0.4 V at IOL = 8 mA. Reflects the state of the differential A/B bus inputs when the receiver is enabled (RE = L). High-impedance when RE = H."
      },
      {
        "number": "2",
        "name": "RE",
        "type": "input",
        "description": "Receiver enable, active-low CMOS input. Drive low to enable receiver output R; drive high to place R in the high-impedance state. VIH ≥ 2 V, VIL ≤ 0.8 V."
      },
      {
        "number": "3",
        "name": "DE",
        "type": "input",
        "description": "Driver enable, active-high CMOS input. Drive high to enable the differential driver on pins A/B; drive low to place A/B in the high-impedance state. VIH ≥ 2 V, VIL ≤ 0.8 V."
      },
      {
        "number": "4",
        "name": "D",
        "type": "input",
        "description": "Driver single-ended CMOS data input. Logic level applied here is transmitted differentially on the A/B bus pins when DE = H. VIH ≥ 2 V, VIL ≤ 0.8 V; input current 0-10 µA."
      },
      {
        "number": "5",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference. All voltages are measured with respect to this pin. Connect to the board ground plane."
      },
      {
        "number": "6",
        "name": "A",
        "type": "bidirectional",
        "description": "Non-inverting M-LVDS bus I/O. Driver output when DE = H (|VAB| typ 480 mV, max 650 mV into 50 Ω, VOS ≈ 0.8-1.2 V); receiver input otherwise. Common-mode input range -1.4 V to 3.8 V. High-impedance when driver is disabled or VCC ≤ 1.5 V."
      },
      {
        "number": "7",
        "name": "B",
        "type": "bidirectional",
        "description": "Inverting M-LVDS bus I/O. Driver output when DE = H (complement of A); receiver input otherwise. Common-mode input range -1.4 V to 3.8 V. High-impedance when driver is disabled or VCC ≤ 1.5 V."
      },
      {
        "number": "8",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive supply, 3.0 V to 3.6 V (3.3 V nominal). Bypass locally with a low-ESR ceramic capacitor to GND. Supply current is 22 mA typ (driver only), 16 mA typ (both enabled, receiver-only 4 mA typ)."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://www.ti.com/lit/ds/symlink/sn65mlvd206.pdf",
        "pages": 31,
        "sha256": "5073de1b180d3c83",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
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        "file": "sn65mlvd206dr.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "sn65mlvd206dr-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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          4.9,
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        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "bdcb1d36a4e869ba82b0a0ac98023e1a310254cca586bc762df53eefc5726e28",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Texas Instruments",
      "Package": "SOIC-8",
      "Category": "Interface",
      "Pins": "8"
    }
  },
  "variants": [
    {
      "mpn": "SN65MLVD206DRD",
      "kind": "packaging"
    },
    {
      "mpn": "SN65MLVD206DR",
      "kind": "packaging"
    }
  ],
  "sections": [
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    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "sn65mlvd206dr"
  ],
  "discovery_pitch": "SN65MLVD206DR (Texas Instruments) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
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    "README.md",
    "sn65mlvd206dr.kicad_sym",
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    "sn65mlvd206dr.glb",
    "sn65mlvd206dr.step",
    "sn65mlvd206dr.lbr",
    "docs/hero.png",
    "docs/sn65mlvd206dr-datasheet.pdf",
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  "visibility": {
    "public": true
  },
  "updated_at": "2026-09-25T06:32:19.919Z"
}