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Generated by kicad-footprint-generator · KiCad file format 20260206

Name	Last commit message	Last updated
docs	sn65mlvd206dr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	5d ago
viewers	sn65mlvd206dr: viewers · Ray	28d ago
package.json	Publish 0.1.0 · Ray	28d ago
page.json	sn65mlvd206dr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray	18h ago
README.md	sn65mlvd206dr: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray	19d ago
sn65mlvd206dr-etched.fit.json	sn65mlvd206dr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	5d ago
sn65mlvd206dr-etched.glb	sn65mlvd206dr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	5d ago
sn65mlvd206dr-etched.step	sn65mlvd206dr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	5d ago
sn65mlvd206dr.glb	Publish 0.1.0 · Ray	28d ago
sn65mlvd206dr.kicad_mod	Publish 0.1.0 · Ray	28d ago
sn65mlvd206dr.kicad_sym	Publish 0.1.0 · Ray	28d ago
sn65mlvd206dr.lbr	Publish 0.1.0 · Ray	28d ago
sn65mlvd206dr.step	Publish 0.1.0 · Ray	28d ago

SN65MLVD206DR

Texas Instruments · LVDS ICs · SOIC-8

SN65MLVD206DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	R	output	Receiver single-ended CMOS output (LVTTL). Drives VOH ≥ 2.4 V at IOH = -8 mA and VOL ≤ 0.4 V at IOL = 8 mA. Reflects the state of the differential A/B bus inputs when the receiver is enabled (RE = L). High-impedance when RE = H.
2	RE	input	Receiver enable, active-low CMOS input. Drive low to enable receiver output R; drive high to place R in the high-impedance state. VIH ≥ 2 V, VIL ≤ 0.8 V.
3	DE	input	Driver enable, active-high CMOS input. Drive high to enable the differential driver on pins A/B; drive low to place A/B in the high-impedance state. VIH ≥ 2 V, VIL ≤ 0.8 V.
4	D	input	Driver single-ended CMOS data input. Logic level applied here is transmitted differentially on the A/B bus pins when DE = H. VIH ≥ 2 V, VIL ≤ 0.8 V; input current 0-10 µA.
5	GND	power_in	Ground reference. All voltages are measured with respect to this pin. Connect to the board ground plane.
6	A	bidirectional	Non-inverting M-LVDS bus I/O. Driver output when DE = H (
7	B	bidirectional	Inverting M-LVDS bus I/O. Driver output when DE = H (complement of A); receiver input otherwise. Common-mode input range -1.4 V to 3.8 V. High-impedance when driver is disabled or VCC ≤ 1.5 V.
8	VCC	power_in	Positive supply, 3.0 V to 3.6 V (3.3 V nominal). Bypass locally with a low-ESR ceramic capacitor to GND. Supply current is 22 mA typ (driver only), 16 mA typ (both enabled, receiver-only 4 mA typ).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-8
Category	Interface
Pins	8

Ordering variants

Same part, different packaging or reel option.

SN65MLVD206DRD
SN65MLVD206DR

CAD (KiCad official)

Symbol: SN65MLVD206DR
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: sn65mlvd206dr-etched.step / sn65mlvd206dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn65mlvd206dr.step / sn65mlvd206dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (31 pp, sha256 5073de1b180d3c83, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF