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Ray si4559ady-t1-ge3: specified limits as data (metadata.characteristics, 60 rows from the datasheet) 338f9c5 16d ago
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{
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  "slug": "si4559ady-t1-ge3",
  "title": "SI4559ADY-T1-GE3",
  "brief": "Vishay Intertech MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
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  "component": {
    "mpn": "SI4559ADY-T1-GE3",
    "manufacturer": "Vishay Intertech",
    "package": "SO-8",
    "pin_count": 8,
    "category": "Transistors/Thyristors",
    "subcategory": "MOSFETs",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590912527578845184",
    "parts": {
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      "footprint": "si4559ady-t1-ge3.kicad_mod",
      "model_3d": "si4559ady-t1-ge3-hero.glb",
      "model_3d_plain": "si4559ady-t1-ge3.glb",
      "model_3d_step": "si4559ady-t1-ge3-etched.step",
      "model_3d_step_plain": "si4559ady-t1-ge3.step",
      "lbr": "si4559ady-t1-ge3.lbr"
    },
    "distributor_links": {
      "lcsc": "C143727",
      "digikey": "SI4559ADY-T1-GE3TR-ND",
      "mouser": "781-SI4559ADY-T1-GE3"
    },
    "distributor_check": {
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      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "SI4559ADY-T1-GE3TR-ND",
        "status": "found",
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      },
      "mouser": {
        "pn": "781-SI4559ADY-T1-GE3",
        "status": "found",
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    },
    "pins": [
      {
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      {
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      {
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        "description": "Drain of the P-channel MOSFET, tied to pin 6 (-60 V drain-source maximum)."
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      {
        "number": "6",
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        "type": "passive",
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      },
      {
        "number": "7",
        "name": "D1",
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        "description": "Drain of the N-channel MOSFET, tied to pin 8 (60 V drain-source maximum)."
      },
      {
        "number": "8",
        "name": "D1",
        "type": "passive",
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      }
    ],
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      "extractor": "extract_pins 0.3",
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        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The pin 5-8 drain labels are scrambled in the extracted text (the 'Top View' numbers and D1/D2 label; Pin types for S and D pins are set to passive and gates to input per KiCad MOSFET convention; the da"
        ],
        "pages_sent": 14,
        "cost_usd": 0.0754,
        "at": "2026-10-09T12:53:38"
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      "Manufacturer": "Vishay Intertech",
      "Package": "SO-8",
      "Category": "Transistors/Thyristors",
      "Pins": "8"
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          "conditions": "VGS = -4.5 V, ID = -0.2 A P-Ch",
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          "name": "Total gate charge at VGS = 4.5 V (N-Ch)",
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          "conditions": "VDD = 30 V, RL = 8.8 Ω, ID 3.4 A, VGEN = 10 V, Rg = 1 Ω N-Ch",
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