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SI4559ADY-T1-GE3

Vishay Intertech · MOSFETs · SO-8

SI4559ADY-T1-GE3 from Vishay Intertech, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S1 passive Source of the N-channel MOSFET (60 V, 5.3 A rated).
2 G1 input Gate of the N-channel MOSFET, rated at ±20 V gate-source maximum.
3 S2 passive Source of the P-channel MOSFET (-60 V, -3.9 A rated).
4 G2 input Gate of the P-channel MOSFET, rated at ±20 V gate-source maximum.
5 D2 passive Drain of the P-channel MOSFET, tied to pin 6 (-60 V drain-source maximum).
6 D2 passive Drain of the P-channel MOSFET, tied to pin 5 (-60 V drain-source maximum).
7 D1 passive Drain of the N-channel MOSFET, tied to pin 8 (60 V drain-source maximum).
8 D1 passive Drain of the N-channel MOSFET, tied to pin 7 (60 V drain-source maximum).

Key specifications

Parameter Value
Manufacturer Vishay Intertech
Package SO-8
Category Transistors/Thyristors
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-source breakdown voltage (N-Ch) VDS 60 V VGS = 0 V, ID = 250 µA N-Ch 2
Drain-source breakdown voltage (P-Ch) VDS -60 V VGS = 0 V, ID = -250 µA P-Ch 2
Gate threshold voltage (N-Ch) VGS(th) 1 3 V VDS = VGS, ID = 250 µA N-Ch 2
Gate threshold voltage (P-Ch) VGS(th) -1 -3 V VDS = VGS, ID = -250 µA P-Ch 2
Gate-body leakage (N-Ch) IGSS 100 nA VDS = 0 V, VGS = ± 20 V N-Ch 2
Gate-body leakage (P-Ch) IGSS -100 nA VDS = 0 V, VGS = ± 20 V P-Ch 2
Zero gate voltage drain current (N-Ch) IDSS 1 µA VDS = 60 V, VGS = 0 V N-Ch 2
Zero gate voltage drain current (P-Ch) IDSS -1 µA VDS = -60 V, VGS = 0 V P-Ch 2
Zero gate voltage drain current at TJ = 55 °C (N-Ch) IDSS 10 µA VDS = 60 V, VGS = 0 V, TJ = 55 °C N-Ch 2
Zero gate voltage drain current at TJ = 55 °C (P-Ch) IDSS -10 µA VDS = -60 V, VGS = 0 V, TJ = 55 °C P-Ch 2
On-state drain current (N-Ch) ID(on) 20 A VDS 5 V, VGS = 10 V N-Ch 2
On-state drain current (P-Ch) ID(on) -25 A VDS -5 V, VGS = -10 V P-Ch 2
Drain-source on-state resistance (N-Ch) RDS(on) 0.058 Ω VGS = 10 V, ID = 4.3 A N-Ch 2
Drain-source on-state resistance (P-Ch) RDS(on) 0.12 Ω VGS = -10 V, ID = -3.1 A P-Ch 2
Drain-source on-state resistance (N-Ch) RDS(on) 0.072 Ω VGS = 4.5 V, ID = 3.9 A N-Ch 2
Drain-source on-state resistance (P-Ch) RDS(on) 0.15 Ω VGS = -4.5 V, ID = -0.2 A P-Ch 2
Total gate charge at VGS = 10 V (N-Ch) Qg 20 nC VDS = 30 V, VGS = 10 V, ID = 4.3 A N-Ch 2
Total gate charge at VGS = -10 V (P-Ch) Qg 22 nC VDS = -30 V, VGS = -10 V, ID = -3.1 A P-Ch 2
Total gate charge at VGS = 4.5 V (N-Ch) Qg 9 nC VDS = 30 V, VGS = 4.5 V, ID = 4.3 A N-Ch 2
Total gate charge at VGS = -4.5 V (P-Ch) Qg 12 nC VDS = -30 V, VGS = -4.5 V, ID = -3.1 A P-Ch 2
Gate resistance (N-Ch) Rg 3 Ω f = 1 MHz N-Ch 2
Gate resistance (P-Ch) Rg 20 Ω f = 1 MHz P-Ch 2
Body diode voltage (N-Ch) VSD 1.2 V IS = 1.7 A N-Ch 3
Body diode voltage (P-Ch) VSD -1.2 V IS = -2 A P-Ch 3
Continuous source-drain diode current (N-Ch) IS 2.6 A TC = 25 °C N-Ch 3
Continuous source-drain diode current (P-Ch) IS -2.8 A TC = 25 °C P-Ch 3
Pulsed diode forward current (N-Ch) ISM 20 A 3
Pulsed diode forward current (P-Ch) ISM -25 A 3
Body diode reverse recovery time (N-Ch) trr 60 ns IF = 1.7 A, di/dt = 100 A/µs, TJ = 25 °C N-Ch 3
Body diode reverse recovery time (P-Ch) trr 50 ns IF = -2 A, di/dt = -100 A/µs, TJ = 25 °C P-Ch 3
Body diode reverse recovery charge (N-Ch) Qrr 50 nC 3
Body diode reverse recovery charge (P-Ch) Qrr 60 nC 3
Turn-on delay time at VGEN = 10 V (N-Ch) td(on) 15 ns VDD = 30 V, RL = 8.8 Ω, ID 3.4 A, VGEN = 10 V, Rg = 1 Ω N-Ch 3
Turn-on delay time at VGEN = -10 V (P-Ch) td(on) 15 ns VDD = -30 V, RL = 12.5 Ω, ID -2.4 A, VGEN = -10 V, Rg = 1 Ω P-Ch 3
Rise time at VGEN = 10 V (N-Ch) tr 25 ns VDD = 30 V, RL = 8.8 Ω, ID 3.4 A, VGEN = 10 V, Rg = 1 Ω N-Ch 3
Rise time at VGEN = -10 V (P-Ch) tr 20 ns VDD = -30 V, RL = 12.5 Ω, ID -2.4 A, VGEN = -10 V, Rg = 1 Ω P-Ch 3
Turn-off delay time at VGEN = 10 V (N-Ch) td(off) 30 ns VDD = 30 V, RL = 8.8 Ω, ID 3.4 A, VGEN = 10 V, Rg = 1 Ω N-Ch 3
Turn-off delay time at VGEN = -10 V (P-Ch) td(off) 55 ns VDD = -30 V, RL = 12.5 Ω, ID -2.4 A, VGEN = -10 V, Rg = 1 Ω P-Ch 3
Fall time at VGEN = 10 V (N-Ch) tf 15 ns VDD = 30 V, RL = 8.8 Ω, ID 3.4 A, VGEN = 10 V, Rg = 1 Ω N-Ch 3
Fall time at VGEN = -10 V (P-Ch) tf 45 ns VDD = -30 V, RL = 12.5 Ω, ID -2.4 A, VGEN = -10 V, Rg = 1 Ω P-Ch 3
Drain-source voltage (N-Ch) VDS 60 V 1
Drain-source voltage (P-Ch) VDS -60 V 1
Gate-source voltage (N-Ch) VGS -20 20 V 1
Gate-source voltage (P-Ch) VGS -20 20 V 1
Continuous drain current (N-Ch) ID 5.3 A TC = 25 °C (TJ = 150 °C) 1
Continuous drain current (P-Ch) ID -3.9 A TC = 25 °C (TJ = 150 °C) 1
Pulsed drain current (N-Ch) IDM 20 A 10 µs pulse width 1
Pulsed drain current (P-Ch) IDM -25 A 10 µs pulse width 1
Maximum power dissipation (N-Ch) PD 3.1 W TC = 25 °C 1
Maximum power dissipation (P-Ch) PD 3.4 W TC = 25 °C 1
Single pulse avalanche current (N-Ch) IAS 11 A L = 0.1 mH 1
Single pulse avalanche current (P-Ch) IAS 15 A L = 0.1 mH 1
Single pulse avalanche energy (N-Ch) EAS 6.1 mJ 1
Single pulse avalanche energy (P-Ch) EAS 11 mJ 1
Operating junction and storage temperature range TJ, Tstg -55 150 °C 1
Maximum junction-to-ambient (N-Ch) RthJA 55 62.5 °C/W t ≤ 10 s 1
Maximum junction-to-ambient (P-Ch) RthJA 53 62.5 °C/W t ≤ 10 s 1
Maximum junction-to-foot (drain) (N-Ch) RthJF 33 40 °C/W Steady state 1
Maximum junction-to-foot (drain) (P-Ch) RthJF 30 37 °C/W Steady state 1
Maximum junction-to-ambient, steady state (N-Ch and P-Ch) RthJA 110 °C/W Steady state (note d) 1

CAD (KiCad official)

  • Symbol: SI4559ADY-T1-GE3
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: si4559ady-t1-ge3-etched.step / si4559ady-t1-ge3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); si4559ady-t1-ge3.step / si4559ady-t1-ge3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Vishay Intertech datasheet (14 pp, sha256 420507069cad3eb3, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF