sgm6132yps8g: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding)
Brief states the pinout check that actually ran (was an unconditional "Datasheet-verified pinout")
sgm6132yps8g: laser-etched CAD + chip hero (factory 2.0.0 backfill)
sgm6132yps8g: backfill missing artifacts (variants)
sgm6132yps8g: publish the laser-etched STEP alongside the bare one
add symbol pin "9" for the exposed thermal pad: the footprint carries the pad and the symbol had none, so it reached no…
pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left)
fix footprint: SOIC-8_3.9x4.9mm_P1.27mm -> SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm (ep_dropped, 8 pins)
sgm6132yps8g: factory component page (tier=lcsc)
Initial commit: component/sgm6132yps8g