# PDTD114ETR

**Nexperia** · Digital Transistors · SOT-23

PDTD114ETR from Nexperia, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | I | input | Input (base) with absolute maximum voltage range from -10 V to +50 V. |
| 2 | GND | power_in | Emitter ground connection. |
| 3 | O | output | Output (collector) with absolute maximum ratings of 50 V collector-emitter voltage and 500 mA output current. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SOT-23 |
| Category | Transistors/Thyristors |
| Pins | 3 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| collector-base voltage | VCBO |  |  | 50 | V | open emitter | 3 |
| collector-emitter voltage | VCEO |  |  | 50 | V | open base | 3 |
| emitter-base voltage | VEBO |  |  | 10 | V | open collector | 3 |
| input voltage positive | VI | -10 |  | 50 | V |  | 3 |
| output current | IO |  |  | 500 | mA |  | 3 |
| total power dissipation | Ptot |  |  | 320 | mW | Tamb ≤ 25 °C; FR4 PCB single-sided 35 µm copper (note 1) | 3 |
| total power dissipation | Ptot |  |  | 460 | mW | FR4 PCB 4-layer copper, standard footprint (note 2) | 3 |
| junction temperature | Tj |  |  | 175 | °C |  | 3 |
| ambient temperature | Tamb | -55 |  | 175 | °C |  | 3 |
| storage temperature | Tstg | -55 |  | 175 | °C |  | 3 |
| thermal resistance from junction to ambient | Rth(j-a) |  |  | 470 | K/W | in free air; FR4 PCB 35 µm copper, single-sided (note 1) | 4 |
| thermal resistance from junction to ambient | Rth(j-a) |  |  | 327 | K/W | in free air; FR4 PCB 4-layer copper (note 2) | 4 |
| collector-base breakdown voltage | V(BR)CBO | 50 |  |  | V | IC = 100 µA; IE = 0 A; Tamb = 25 °C | 5 |
| collector-emitter breakdown voltage | V(BR)CEO | 50 |  |  | V | IC = 10 mA; IB = 0 A; Tamb = 25 °C | 5 |
| collector-base cut-off current | ICBO |  |  | 100 | nA | VCB = 40 V; IE = 0 A; Tamb = 25 °C | 5 |
| collector-emitter cut-off current | ICEO |  |  | 0.5 | µA | VCE = 50 V; IB = 0 A; Tamb = 25 °C | 5 |
| emitter-base cut-off current | IEBO |  |  | 0.4 | mA | VEB = 5 V; IC = 0 A; Tamb = 25 °C | 5 |
| DC current gain | hFE | 70 |  |  |  | VCE = 5 V; IC = 50 mA; Tamb = 25 °C | 5 |
| collector-emitter saturation voltage | VCEsat |  |  | 100 | mV | IC = 50 mA; IB = 2.5 mA; Tamb = 25 °C | 5 |
| off-state input voltage | VI(off) | 0.6 | 1 | 1.5 | V | VCE = 5 V; IC = 100 µA; Tamb = 25 °C | 5 |
| on-state input voltage | VI(on) | 1 | 1.9 | 3 | V | VCE = 0.3 V; IC = 20 mA; Tamb = 25 °C | 5 |
| bias resistor 1 (input) | R1 | 7 | 10 | 13 | kΩ | See Section 11: Test information (Table 8 resistor test conditions) | 5 |
| bias resistor ratio | R2/R1 | 0.9 | 1 | 1.1 |  | See Section 11: Test information (Table 8 resistor test conditions) | 5 |

## CAD (KiCad official)

- Symbol: `PDTD114ETR`
- Footprint: `Package_TO_SOT_SMD:SOT-23`
- 3D model: SOT-23 (KiCad packages3D, STEP)
- 3D model files: `pdtd114etr-etched.step` / `pdtd114etr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `pdtd114etr.step` / `pdtd114etr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Nexperia datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588912965051015168) (13 pp, sha256 `00cf6a4f5014c14d`, retrieved 2026-09-21, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/pdtd114etr-datasheet.pdf)