component
MAX8556ETE+T
Public Made by Adomby adom
Analog Devices Inc Maxim Integrated Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, TQFN-16-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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"description": "Analog Devices Inc Maxim Integrated Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, TQFN-16-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
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"power management (pmic)",
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"component": {
"mpn": "MAX8556ETE+T",
"manufacturer": "Analog Devices Inc Maxim Integrated",
"package": "TQFN-16-EP(5x5)",
"pin_count": 17,
"category": "Power Management (PMIC)",
"subcategory": "Voltage Regulators - Linear, Low Drop Out (LDO) Regulators",
"datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588912372916764672",
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"distributor_links": {
"lcsc": "C516779"
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"distributor_check": {
"checked_at": "2026-10-18T15:24:42Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": null,
"status": "quota"
},
"mouser": {
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"status": "quota"
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},
"pins": [
{
"number": "1",
"name": "IN",
"type": "power_in",
"description": "LDO input, to be connected to a 1.425V to 3.6V input voltage and bypassed with a 22µF ceramic capacitor to GND."
},
{
"number": "2",
"name": "IN",
"type": "power_in",
"description": "LDO input, to be connected to a 1.425V to 3.6V input voltage and bypassed with a 22µF ceramic capacitor to GND."
},
{
"number": "3",
"name": "IN",
"type": "power_in",
"description": "LDO input, to be connected to a 1.425V to 3.6V input voltage and bypassed with a 22µF ceramic capacitor to GND."
},
{
"number": "4",
"name": "IN",
"type": "power_in",
"description": "LDO input, to be connected to a 1.425V to 3.6V input voltage and bypassed with a 22µF ceramic capacitor to GND."
},
{
"number": "5",
"name": "IN",
"type": "power_in",
"description": "LDO input, to be connected to a 1.425V to 3.6V input voltage and bypassed with a 22µF ceramic capacitor to GND."
},
{
"number": "6",
"name": "IN",
"type": "power_in",
"description": "LDO input, to be connected to a 1.425V to 3.6V input voltage and bypassed with a 22µF ceramic capacitor to GND."
},
{
"number": "7",
"name": "OUT",
"type": "power_out",
"description": "LDO output, to be bypassed with 2 x 10µF ceramic capacitors to GND; a smaller capacitance can be used if the maximum load current is less than 4A."
},
{
"number": "8",
"name": "OUT",
"type": "power_out",
"description": "LDO output, to be bypassed with 2 x 10µF ceramic capacitors to GND; a smaller capacitance can be used if the maximum load current is less than 4A."
},
{
"number": "9",
"name": "OUT",
"type": "power_out",
"description": "LDO output, to be bypassed with 2 x 10µF ceramic capacitors to GND; a smaller capacitance can be used if the maximum load current is less than 4A."
},
{
"number": "10",
"name": "OUT",
"type": "power_out",
"description": "LDO output, to be bypassed with 2 x 10µF ceramic capacitors to GND; a smaller capacitance can be used if the maximum load current is less than 4A."
},
{
"number": "11",
"name": "OUT",
"type": "power_out",
"description": "LDO output, to be bypassed with 2 x 10µF ceramic capacitors to GND; a smaller capacitance can be used if the maximum load current is less than 4A."
},
{
"number": "12",
"name": "POK",
"type": "output",
"description": "Open-drain power-OK output that is high impedance when VOUT is within ±10% of nominal and pulls low when VOUT is outside that range or when EN is low; connect a resistor to a logic supply of less than 3.6V."
},
{
"number": "13",
"name": "FB",
"type": "input",
"description": "Feedback input regulated to 0.5V; connect to the center tap of a resistor divider from the output to GND to set the output voltage."
},
{
"number": "14",
"name": "GND",
"type": "power_in",
"description": "Ground."
},
{
"number": "15",
"name": "N.C.",
"type": "unconnected",
"description": "Not connected internally; connect to GND or leave unconnected."
},
{
"number": "16",
"name": "EN",
"type": "input",
"description": "Enable input; connect to GND or a logic low to shut the device down, and to IN or a logic high for normal operation."
},
{
"number": "17",
"name": "EP",
"type": "passive",
"description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The exposed paddle is listed as '—' with the label EP in the pin table, not as a numbered pin. It is; Pin 12 is shared between MAX8556 (POK) and MAX8557 (POR). The MPN is MAX8556, so the name is POK; th; Pin 1-6 bypass is given as 22µF in the pin table, but the Capacitor Selection section (page 10) reco",
"exposed pad 17 added from the footprint",
"dropped thermal pad ['EP'] absent from footprint"
],
"pages_sent": 12,
"cost_usd": 0.0679,
"at": "2026-10-18T15:24:27"
},
"datasheet": {
"url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588912372916764672",
"pages": 12,
"sha256": "4fa6f5030655818e",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 17,
"described": 17,
"cites_pages": true,
"refuses_to_fabricate": true
}
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