main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 4h ago
viewers max8556ete-t: viewers · Ray 4h ago
max8556ete-t-etched.glb Publish 0.1.0 · Ray 4h ago
max8556ete-t-etched.step max8556ete-t: factory component page (tier=lcsc) · Ray 4h ago
max8556ete-t-hero.glb max8556ete-t: hero GLB from the etched model (keeps the MPN mark) · Ray 4h ago
max8556ete-t-hero.overlay.json Publish 0.1.0 · Ray 4h ago
max8556ete-t.glb Publish 0.1.0 · Ray 4h ago
max8556ete-t.kicad_mod Publish 0.1.0 · Ray 4h ago
max8556ete-t.kicad_sym Publish 0.1.0 · Ray 4h ago
max8556ete-t.lbr Publish 0.1.0 · Ray 4h ago
max8556ete-t.step Publish 0.1.0 · Ray 4h ago
package.json Publish 0.1.0 · Ray 4h ago
page.json Set visibility: public · Ray 4h ago
README.md Publish 0.1.0 · Ray 4h ago

MAX8556ETE+T

Analog Devices Inc Maxim Integrated · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · TQFN-16-EP(5x5)

MAX8556ETE+T from Analog Devices Inc Maxim Integrated, in a TQFN-16-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in LDO input, to be connected to a 1.425V to 3.6V input voltage and bypassed with a 22µF ceramic capacitor to GND.
2 IN power_in LDO input, to be connected to a 1.425V to 3.6V input voltage and bypassed with a 22µF ceramic capacitor to GND.
3 IN power_in LDO input, to be connected to a 1.425V to 3.6V input voltage and bypassed with a 22µF ceramic capacitor to GND.
4 IN power_in LDO input, to be connected to a 1.425V to 3.6V input voltage and bypassed with a 22µF ceramic capacitor to GND.
5 IN power_in LDO input, to be connected to a 1.425V to 3.6V input voltage and bypassed with a 22µF ceramic capacitor to GND.
6 IN power_in LDO input, to be connected to a 1.425V to 3.6V input voltage and bypassed with a 22µF ceramic capacitor to GND.
7 OUT power_out LDO output, to be bypassed with 2 x 10µF ceramic capacitors to GND; a smaller capacitance can be used if the maximum load current is less than 4A.
8 OUT power_out LDO output, to be bypassed with 2 x 10µF ceramic capacitors to GND; a smaller capacitance can be used if the maximum load current is less than 4A.
9 OUT power_out LDO output, to be bypassed with 2 x 10µF ceramic capacitors to GND; a smaller capacitance can be used if the maximum load current is less than 4A.
10 OUT power_out LDO output, to be bypassed with 2 x 10µF ceramic capacitors to GND; a smaller capacitance can be used if the maximum load current is less than 4A.
11 OUT power_out LDO output, to be bypassed with 2 x 10µF ceramic capacitors to GND; a smaller capacitance can be used if the maximum load current is less than 4A.
12 POK output Open-drain power-OK output that is high impedance when VOUT is within ±10% of nominal and pulls low when VOUT is outside that range or when EN is low; connect a resistor to a logic supply of less than 3.6V.
13 FB input Feedback input regulated to 0.5V; connect to the center tap of a resistor divider from the output to GND to set the output voltage.
14 GND power_in Ground.
15 N.C. unconnected Not connected internally; connect to GND or leave unconnected.
16 EN input Enable input; connect to GND or a logic low to shut the device down, and to IN or a logic high for normal operation.
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices Inc Maxim Integrated
Package TQFN-16-EP(5x5)
Category Power Management (PMIC)
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Voltage Range 1.425 3.6 V 2
Input Undervoltage Lockout (VIN rising) 1.3 1.35 1.4 V VIN rising, 70mV hysteresis 2
Input Undervoltage Lockout (VIN falling) 1.23 1.28 1.33 V VIN falling 2
Output Voltage Range 0.5 3.4 V 2
Line Regulation -0.15 0 0.15 %/V VIN = 1.425V to 3.6V, VOUT = 1.225V 2
Dropout Voltage 100 200 mV VIN = 1.425V, IOUT = 4A, VFB = 480mV 2
Regulated Output-Voltage Current Limit 5 7 9 A VIN = 3.6V, VOUT = 3V, VFB = 460mV 2
Load Capacitance 16 120 µF ESR < 50mA (Note 3) 2
FB Threshold Accuracy 495 500 505 mV VOUT = 1.225V to 3V, VIN = VOUT + 0.2V to 3.6V, IOUT = 2mA to 4A (Note 4) 2
FB Input Bias Current 0.001 1 µA VFB = 0.5V, VIN = 3.6V 2
GND Supply Current 800 1600 µA VIN = 1.425V to 3.6V, VOUT = 1.225V 3
GND Supply Current (Dropout) 1000 2000 µA VIN = 3.6V, VFB = 480mV 3
GND Shutdown Current 150 µA VIN = 3.6V, EN = GND 3
FB Power-OK Fault Threshold (FB high) 540 550 560 mV FB moving out of regulation, VIN = 1.425V to 3.6V, 10mV hysteresis 3
FB Power-OK Fault Threshold (FB low) 440 450 460 mV FB moving out of regulation, VIN = 1.425V to 3.6V, 10mV hysteresis 3
POK Output Voltage, Low 25 200 mV VFB = 0.4V or 0.6V, IPOK = 2mA 3
POK Output Current, High 0.001 1 µA VPOK = 3.6V VFB = 0.5 3
Enable Input Bias Current -1 1 µA VEN = 0V or 3.6V 3
POR FB Power-On Reset Fault Threshold 440 450 460 mV FB falling, VIN = 1.425V to 3.6V, 10mV hysteresis 3
POR Output Voltage, Low 25 200 mV VFB = 0.4V, IPOR = 2mA 3
POR Output Current, High 0.001 1 µA VPOR = 3.6V, VFB = 0.5V 3
POK Delay Time 25 50 100 µs FB rising to POK high 3
POR Rising Delay Time 100 140 200 ms FB rising to POR high impedance 3
Absolute Maximum: IN, EN, POK, POR to GND -0.3 4 V 2
Absolute Maximum: FB, OUT to GND (max is VIN + 0.3V) -0.3 V 2
Operating Temperature Range -40 85 °C 2
Junction Temperature TJ 150 °C 2
Storage Temperature Range -65 150 °C 2
Lead Temperature 300 °C soldering, 10s 2
Thermal-Shutdown Threshold (TJ rising) 160 °C Output on and off 3
Thermal-Shutdown Threshold (TJ falling) 115 °C Output on and off 3
Soft-Start Time 100 µs 3
Load Regulation 0.1 %/A IOUT = 2mA to 4A 2
Enable Input Threshold (EN rising) 1.25 V VIN = 1.425V to 3.6V 3
Enable Input Threshold (EN falling) 0.4 V VIN = 1.425V to 3.6V 3
Thermal Resistance, Junction-to-Case (16-pin TQFN) θJC 1.7 °C/W junction to case, 16-pin TQFN 11

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper (1.7°C/W for the 16-pin TQFN) θCA = the thermal resistance from the case to the sur￾rounding air through the PCB, copper traces, and the 11

CAD (KiCad official)

  • Symbol: MAX8556ETE+T
  • Footprint: Package_DFN_QFN:QFN-16-1EP_5x5mm_P0.8mm_EP2.7x2.7mm
  • 3D model: TQFN-16-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: max8556ete-t-etched.step / max8556ete-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); max8556ete-t.step / max8556ete-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices Inc Maxim Integrated datasheet (12 pp, sha256 4fa6f5030655818e, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF