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FU6572N

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Fortior Tech Microcontrollers (MCU/MPU/SOC), QFN-40-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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FU6572N

Fortior Tech · Microcontrollers (MCU/MPU/SOC) · QFN-40-EP(5x5)

FU6572N from Fortior Tech, in a QFN-40-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VSU power_in 6N pre-driver U-phase bootstrap return reference for the U high-side driver.
2 HU output 6N pre-driver U-phase high-side PWM output.
3 VBU power_in 6N pre-driver U-phase high-side bootstrap supply.
4 VSV power_in 6N pre-driver V-phase bootstrap return reference for the V high-side driver.
5 HV output 6N pre-driver V-phase high-side PWM output.
6 VBV power_in 6N pre-driver V-phase high-side bootstrap supply.
7 VSW power_in 6N pre-driver W-phase bootstrap return reference for the W high-side driver.
8 HW output 6N pre-driver W-phase high-side PWM output.
9 VBW power_in 6N pre-driver W-phase high-side bootstrap supply.
10 VDD5 power_out VDD5 supply pin, with an external 1uF to 4.7uF capacitor.
11 VSS power_in Digital ground.
12 P4.7/TIM3S2/RXD2S2/RSTN/FICEK input P4.7 input (GPIO); remapped Timer3 input, remapped UART2 RXD input, external reset input with internal pull-up, and FICE clock pin.
13 P4.5/AD14 bidirectional GPIO configurable as INT1 external interrupt input; ADC channel 14 input.
14 P1.2/TIM4S2/TXD2S2/FICED bidirectional GPIO configurable as INT1 input; remapped Timer4 input/output, remapped UART2 TXD output, FICE data port.
15 P1.3/HBIAS/C1PS/A3O/AD12 bidirectional GPIO configurable as INT1 input; Hall bias supply switched internally to VDD5, remapped CMP1 positive input, AMP3 output, ADC channel 12 input.
16 P1.4/C0P/A3M/AD10/HAL0S bidirectional GPIO configurable as INT1 input; CMP0 positive input, AMP3 negative input, ADC channel 10 input, remapped Hall-IC0 logic input.
17 P1.5/C0M/C2PS/A3P/AD13 bidirectional GPIO configurable as INT1 input; CMP0 negative input, remapped CMP2 positive input, AMP3 positive input, ADC channel 13 input.
18 P1.6/C1P/A1P/AD9/HAL1S bidirectional GPIO configurable as INT1 input; CMP1 positive input, AMP1 positive input, ADC channel 9 input, remapped Hall-IC1 logic input.
19 P1.7/C1M/A1M bidirectional GPIO configurable as INT1 input; CMP1 negative input and AMP1 negative input.
20 P2.1/C2P/A2P/AD8/HAL2S bidirectional GPIO; CMP2 positive input, AMP2 positive input, ADC channel 8 input, remapped Hall-IC2 logic input.
21 P2.2/C2M/A2M bidirectional GPIO; CMP2 negative input and AMP2 negative input.
22 P2.4/AD2 bidirectional GPIO; ADC channel 2 input, usable for bus voltage sampling.
23 P2.5/AD3 bidirectional GPIO; ADC channel 3 input.
24 P2.6/C3M/DA0/AD11 bidirectional GPIO; CMP3 negative input, DAC0 unbuffered output, ADC channel 11 input.
25 P3.0/A0M bidirectional GPIO; AMP0 negative input.
26 P3.1/A0P bidirectional GPIO; AMP0 positive input.
27 P3.3/AD6 bidirectional GPIO; ADC channel 6 input.
28 P3.4/AD7/C3PS/C4MS bidirectional GPIO; ADC channel 7 input (with AMP_CR0[CP_EN]=1 AMP0 output goes via internal 50k to P3.4, needing external 1uF, for average bus current), remapped CMP3 positive and CMP4 negative inputs.
29 P3.5/VREF bidirectional GPIO; ADC external reference input or internal VREF output, with external series R (33 ohm) + C (1uF to 4.7uF) to VSS.
30 P3.6/HAL2/RXD2 bidirectional GPIO; Hall-IC2 logic input; UART2 RXD input in two-wire mode or TXD output/RXD input in single-wire mode.
31 P0.0/TIM4S/TXD2S/SDA bidirectional GPIO configurable as INT0 input; remapped Timer4 input/output, remapped UART2 TXD output, I2C SDA configurable as open-drain.
32 P0.1/DBG/TIM4/TIM3S/RXD2S/SCL bidirectional GPIO configurable as INT0 input; Debug port, Timer4 input/output, remapped Timer3 input/output, remapped UART2 RXD/single-wire pin, I2C SCL open-drain clock.
33 P0.5/TXD/SCLK bidirectional GPIO configurable as INT0 input; UART1 TXD output and SPI clock SCLK.
34 P0.6/RXD/MOSI bidirectional GPIO configurable as INT0 input; UART1 RXD input (or single-wire TXD/RXD) and SPI MOSI.
35 P1.1/TIM3 bidirectional GPIO configurable as INT0/INT1 input; Timer3 input or output.
36 VCC power_in VCC supply, with an external 1uF to 4.7uF capacitor.
37 VSS power_in Power ground.
38 LU output 6N pre-driver U-phase low-side PWM output.
39 LV output 6N pre-driver V-phase low-side PWM output.
40 LW output 6N pre-driver W-phase low-side PWM output.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Fortior Tech
Package QFN-40-EP(5x5)
Category Embedded Processors & Controllers
Pins 41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating junction temperature TJ -40 125 ℃ 80
Storage temperature Tstg -55 125 ℃ 80
VDD5 to VSS voltage VDD5 -0.3 6.5 V 80
RSTN, GPIO to VSS voltage (max is VDD5 + 0.3) -0.3 V 80
VCC to VSS voltage VCC -0.3 25 V 80
VB_(UVW) voltage VB_(UVW) -0.3 110 V 80
VCC operating voltage VCC 7 20 V TA = 25℃, VDD5 = 5V 83
VDD5 operating voltage VDD5 3 5.5 V TA = 25℃, VDD5 = 5V 83
Ivcc operating current Ivcc 12 mA VCC = 15V 83
Ivcc standby current Ivcc 5 mA VCC = 15V 83
Ivcc sleep current Ivcc 180 μA VCC = 15V 83
Operating ambient temperature TA -40 85 ℃ 83
Operating ambient temperature (derated) TA 105 ℃ VCC ≤ 15V & Ivcc ≤ 30mA 83
GPIO pull-up resistor 33 kΩ VDD5 = 5V 86
GPIO pull-up resistor (P0[1:0], P1[6:3], P2[1], P3[6]) 5.6 kΩ VDD5 = 5V 86
GPIO pull-down resistor (P0[1], P1[1], P4[7]) 30 kΩ VDD5 = 5V 86
High-level output peak current 0.8 A VCC = 15V 91
Low-level output peak current 0.8 A VCC = 15V 91
VBU,VBV,VBW floating voltage VBU,VBV,VBW 90 V 91
VBU to VSU, VBV to VSV, VBW to VSW voltage 20 V 91
VDD5 output voltage VDD5 5 V VCC = 15V, internal LDO output configured 92
VCC quiescent current 200 500 μA Input is 0 or 5V 92
VCC UVLO turn-on voltage 4.3 4.8 5.3 V 92
VCC UVLO turn-off voltage 4 4.5 5 V 92
VCC UVLO hysteresis 0.2 0.3 V 92
Output rise time 30 70 ns 1nF load, 10% to 90% 92
Output fall time 30 70 ns 1nF load, 90% to 10% 92
Dead time DT 100 ns 92
ADC INL INL 2 LSB 12-bit mode 94
ADC DNL DNL 1.5 LSB 12-bit mode 94
ADC offset error OFFSET 6 LSB 12-bit mode 95
ADC SNR SNR 70.8 dB fIN = 350kHz 95
ADC ENOB ENOB 10.5 Bit fIN = 350kHz 95
ADC SFDR SFDR 68.2 dB fIN = 350kHz 95
ADC THD THD 67 dB fIN = 350kHz 95
ADC input resistance RIN 800 Ω 95
ADC input capacitance CIN 30 pF 95
ADC conversion time 13 ADCLK ADCLK = 12MHz 95
ADC sampling time 3 63 ADCLK ADCLK = 12MHz 95
VREF VREF 5 V VREF_CR[VREFVSEL] = 01, TA = -40℃ ~ 85℃, VDD5 = 5V 95
Op-amp input offset voltage VOS 5 10 mV TA = 25℃ 97
Op-amp open-loop gain AOL 80 dB RL = 100kΩ 97
Op-amp unity-gain bandwidth UGBW 6 10 MHz CL = 40pF 97
Op-amp slew rate SR 10 15 V/μs CL = 40pF 98
Op-amp gain 2 1.88 2 2.12 AMP_CR1[AMP0_GAIN] = 001 98
Op-amp gain 4 3.76 4 4.24 AMP_CR1[AMP0_GAIN] = 010 98
Op-amp gain 8 7.5 8 8.5 AMP_CR1[AMP0_GAIN] = 011 98
Op-amp gain 16 15 16 17 AMP_CR1[AMP0_GAIN] = 100 98
BEMF internal resistor 5.4 6.8 8.2 kΩ 98
BEMF internal resistor relative accuracy 1 % 98
System clock frequency 23.5 24 24.5 MHz TA = -40℃ ~ 85℃, VDD5 = 5V 98
Low-speed clock frequency 29 32.8 37 kHz TA = -40℃ ~ 85℃, VDD5 = 5V 98
RSTN minimum low-level reset time 50 μs 98
VDD5 low-voltage reset voltage 2.8 3 3.2 V LVR = 3.0V 98
LDO VDD5 voltage VDD5 4.7 5 5.3 V VCC = 7V ~ 20V 99
Thermal resistance junction-ambient (2S2P) θJA 52.4 ℃/W JEDEC standard, 2S2P PCB 99
Thermal resistance junction-ambient (1S0P) θJA 72.2 ℃/W JEDEC standard, 1S0P PCB 99
Thermal resistance junction-case θJC 17 ℃/W JEDEC standard, 1S0P PCB 99

CAD (KiCad official)

  • Symbol: FU6572N
  • Footprint: Package_DFN_QFN:QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm
  • 3D model: QFN-40-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: fu6572n-etched.step / fu6572n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); fu6572n.step / fu6572n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Fortior Tech datasheet (399 pp, sha256 7f4db0deacdfc220, retrieved 2026-10-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF