component
FU6572N
Public Made by Adomby adom
Fortior Tech Microcontrollers (MCU/MPU/SOC), QFN-40-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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<text x="0" y="3.450" size="1.27" layer="25" align="bottom-center">>NAME</text>
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<pin name="VSU" x="-17.78" y="25.4" length="middle" direction="pwr"/>
<pin name="HU" x="-17.78" y="22.86" length="middle" direction="out"/>
<pin name="VBU" x="-17.78" y="20.32" length="middle" direction="pwr"/>
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<pin name="EP" x="17.78" y="22.86" length="middle" direction="pas" rot="R180"/>
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<pin name="VCC" x="17.78" y="10.16" length="middle" direction="pwr" rot="R180"/>
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<pin name="P2.4/AD2" x="17.78" y="-25.4" length="middle" direction="io" rot="R180"/>
</symbol>
</symbols>
<devicesets>
<deviceset name="FU6572N" prefix="U">
<description></description>
<gates>
<gate name="G$1" symbol="FU6572N" x="0" y="0"/>
</gates>
<devices>
<device name="" package="QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm">
<connects>
<connect gate="G$1" pin="VSU" pad="1"/>
<connect gate="G$1" pin="HU" pad="2"/>
<connect gate="G$1" pin="VBU" pad="3"/>
<connect gate="G$1" pin="VSV" pad="4"/>
<connect gate="G$1" pin="HV" pad="5"/>
<connect gate="G$1" pin="VBV" pad="6"/>
<connect gate="G$1" pin="VSW" pad="7"/>
<connect gate="G$1" pin="HW" pad="8"/>
<connect gate="G$1" pin="VBW" pad="9"/>
<connect gate="G$1" pin="VDD5" pad="10"/>
<connect gate="G$1" pin="VSS" pad="11"/>
<connect gate="G$1" pin="P4.7/TIM3S2/RXD2S2/RSTN/FICEK" pad="12"/>
<connect gate="G$1" pin="P4.5/AD14" pad="13"/>
<connect gate="G$1" pin="P1.2/TIM4S2/TXD2S2/FICED" pad="14"/>
<connect gate="G$1" pin="P1.3/HBIAS/C1PS/A3O/AD12" pad="15"/>
<connect gate="G$1" pin="P1.4/C0P/A3M/AD10/HAL0S" pad="16"/>
<connect gate="G$1" pin="P1.5/C0M/C2PS/A3P/AD13" pad="17"/>
<connect gate="G$1" pin="P1.6/C1P/A1P/AD9/HAL1S" pad="18"/>
<connect gate="G$1" pin="P1.7/C1M/A1M" pad="19"/>
<connect gate="G$1" pin="P2.1/C2P/A2P/AD8/HAL2S" pad="20"/>
<connect gate="G$1" pin="P2.2/C2M/A2M" pad="21"/>
<connect gate="G$1" pin="EP" pad="41"/>
<connect gate="G$1" pin="LW" pad="40"/>
<connect gate="G$1" pin="LV" pad="39"/>
<connect gate="G$1" pin="LU" pad="38"/>
<connect gate="G$1" pin="VSS@2" pad="37"/>
<connect gate="G$1" pin="VCC" pad="36"/>
<connect gate="G$1" pin="P1.1/TIM3" pad="35"/>
<connect gate="G$1" pin="P0.6/RXD/MOSI" pad="34"/>
<connect gate="G$1" pin="P0.5/TXD/SCLK" pad="33"/>
<connect gate="G$1" pin="P0.1/DBG/TIM4/TIM3S/RXD2S/SCL" pad="32"/>
<connect gate="G$1" pin="P0.0/TIM4S/TXD2S/SDA" pad="31"/>
<connect gate="G$1" pin="P3.6/HAL2/RXD2" pad="30"/>
<connect gate="G$1" pin="P3.5/VREF" pad="29"/>
<connect gate="G$1" pin="P3.4/AD7/C3PS/C4MS" pad="28"/>
<connect gate="G$1" pin="P3.3/AD6" pad="27"/>
<connect gate="G$1" pin="P3.1/A0P" pad="26"/>
<connect gate="G$1" pin="P3.0/A0M" pad="25"/>
<connect gate="G$1" pin="P2.6/C3M/DA0/AD11" pad="24"/>
<connect gate="G$1" pin="P2.5/AD3" pad="23"/>
<connect gate="G$1" pin="P2.4/AD2" pad="22"/>
</connects>
<technologies><technology name=""/></technologies>
</device>
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