# Thermal comparison on the actual connected pour geometry (cand3 pours; cand5 differs only in the SYS bottom island)

Model: thermal/plate_model.py + thermal/region_analysis.py. 2-D conduction in 35 um copper (k = 385 W/mK) on a 0.1 mm grid over the connected copper region of each net/layer, source cells (the hot part's pads on that net) fixed at 65 C, ambient and radiative surroundings 25 C, loss from the exposed face only: convection h = 3 / 5 / 10 W/m2K plus radiation with finish emissivity. Solder mask: 25 um LPI, k = 0.25 W/mK, emissivity 0.90 (film resistance in series). Bare finishes: ENIG 0.10, HASL/tin 0.15, oxidised copper 0.60. These are comparison assumptions, not measurements and not a power rating; package, vias, FR4, the other layers and any enclosure are omitted, so the watts below are the exposed-copper contribution at a fixed 65 C source, not the board's total dissipation or a junction temperature.

| net | layer | connected area mm2 | mask (eps 0.90) h=3/5/10 W | bare ENIG (eps 0.10) h=3/5/10 W | bare HASL (0.15) h=5 | oxidised Cu (0.60) h=5 | T_min in region (mask, h=5) |
|---|---|---|---|---|---|---|---|
| SYS | L1 | 35.58 | 0.013 / 0.015 / 0.021 | 0.005 / 0.008 / 0.014 | 0.008 | 0.013 | 61.4 C |
| VBUS | L1 | 98.32 | 0.036 / 0.044 / 0.061 | 0.015 / 0.022 / 0.041 | 0.023 | 0.036 | 51.7 C |
| VBUS | L16 | 104.54 | 0.038 / 0.046 / 0.065 | 0.015 / 0.023 / 0.043 | 0.025 | 0.038 | 61.1 C |
| BAT | L1 | 18.68 | 0.007 / 0.008 / 0.011 | 0.003 / 0.004 / 0.007 | 0.004 | 0.007 | 61.9 C |
| PMID | L1 | 8.82 | 0.003 / 0.004 / 0.006 | 0.001 / 0.002 / 0.004 | 0.002 | 0.003 | 63.7 C |
| PGND | L1 | 138.09 | 0.048 / 0.058 / 0.079 | 0.020 / 0.030 / 0.054 | 0.032 | 0.048 | 60.9 C |
| VBAT | L1 | 26.75 | 0.010 / 0.013 / 0.018 | 0.004 / 0.006 / 0.011 | 0.007 | 0.010 | 64.3 C |
| VBAT | L16 | 22.83 | 0.009 / 0.011 / 0.015 | 0.003 / 0.005 / 0.010 | 0.006 | 0.009 | 64.5 C |
| VAC1 | L1 | 114.27 | 0.043 / 0.051 / 0.072 | 0.017 / 0.026 / 0.048 | 0.028 | 0.042 | 62.5 C |
| VAC1 | L16 | 60.25 | 0.022 / 0.027 / 0.038 | 0.009 / 0.013 / 0.025 | 0.014 | 0.022 | 62.1 C |
| VAC2 | L1 | 89.76 | 0.034 / 0.040 / 0.057 | 0.013 / 0.020 / 0.038 | 0.022 | 0.033 | 62.0 C |
| VAC2 | L16 | 116.02 | 0.043 / 0.052 / 0.074 | 0.017 / 0.026 / 0.049 | 0.028 | 0.043 | 62.9 C |

Sum over the listed regions at h = 5: mask-covered 0.368 W vs bare ENIG 0.187 W. Removing the mask on this board would REDUCE the calculated exposed-face dissipation because bright ENIG/HASL copper radiates far less (eps 0.1-0.15) than the mask (0.9); only heavily oxidised bare copper approaches the masked value. The mask film's own resistance is negligible at these heat fluxes.

Decision: keep the solder mask over all pours (no mask openings added). Exposing copper would be justified only for a contact heatsink or thermal-interface path, which is a separate conduction problem (electrical isolation, assembly) not evaluated here. Neck/via bottlenecks: the IC's heat enters through 0.2 mm-wide pin escapes (SYS, PMID, VBUS, BAT, PGND) before reaching the pours; the plate model's fixed 65 C source on those pads hides that neck, so the real spreading is worse than these figures. Energy balance and mesh checks: thermal/plate_model.py self-test (uniform plate matches the analytic value).