# Planner method (own code, no external autorouter)

Location: planner/ (brd.py parser, geom.py raster, route.py A*, run.py driver, finalize.py rip-up/dog-bone repair,
snap.py Fusion-connectivity conformance, check.py exact geometry checker, pours.py/pourplan.py pour prediction and
expansion, emit.py EAGLE command emitter/BRD injector, validate.py native validation, record_take.py recorded replay).
Not used: Freerouting, Fusion's autorouter, fusion_plan_route (the bridge's own A*), any Astra plan or coordinate.

Inputs: the stripped board (native RIPUP of the reference copy, exported by Fusion; byte-equivalent in pads/elements/
rules to my offline strip), the schematic net membership, the inherited design rules, BQ25792/CSD17581 datasheet facts.

Geometry model: 0.05 mm grid, four copper layers. Two rasters per layer: an exact centre-test raster (connectivity,
sources/targets) and a one-cell-dilated raster (clearance). Pads, plated-hole rings (EAGLE restring model), MOSFET tab
polygonshapes, tRestrict areas and board-edge keep-in are fixed obstacles. Clearance for a trace of width w to other-net
copper: dilate(other copper, w/2 + 0.1 mm + margin), strict inequality. Same-net copper that is not the current
source/target is kept 0.25 mm away (the inherited Same-net track spacing rule). Via legality: ring + 0.1 mm to other
copper on all four layers, drill-to-drill/hole 0.2 mm, 0.1 mm to any SMD pad (Fusion same-signal rule).

Search: A* over (layer, cell) with 8 directions (H/V cost 1, diagonal sqrt2), a bend penalty and a via penalty; a
weighted heuristic (1.2). Multi-pin nets connect the nearest unconnected pad to the exact connected copper
(flood-fill on the exact raster, propagated through vias and plated holes). Net order: switch nodes and bootstrap
first, then IC1 fan-out sides in a nested order, then power, then the rest, PGND last (L2 preferred, cheap vias).

Fan-out discipline for the 0.4 mm-pitch QFN: 0.15 mm pin stubs (0.2 mm for power pins), corner duplicate pads joined
with L-shaped joiners, reserved escape corridors per pin on the top layer (1.6 mm) and a via-landing corridor on the
inner/bottom layers (0.5 x 2.5 mm) that other nets may not enter until the pin is routed, 0.4/0.2 mm signal vias,
0.6/0.3 mm power vias, wide power escapes stay narrow until the neighbours can fan out.

Repair: fallback widths, exact-geometry dog-bone placement (shapely), and local rip-up/re-route of the nearest
blocking neighbours when a pin is boxed in. Post-processing: collinear-vertex removal, numeric angle audit (0/45/90/135
only), Fusion connectivity conformance (split wires at crossed same-net pads/vias, T-junction vertices, endpoint into
pad centres and MOSFET tab anchor pads), overlapping same-net via removal.

Pours: per-net region boxes (VBUS, VAC1, VAC2, VBAT, SYS, BAT, PMID, SRCTOSRC, SRCTOSRC1 on L1/L16; PGND on all four
layers at lowest priority), stitching vias at the bulk-capacitor pads, predicted fill = region minus other-net copper
dilated by the 0.2 mm isolate, islands excluded (orphans off), then a greedy expansion pass growing each region box by
1 mm steps while its connected area grows and no other power pour loses area. Areas are unions with drill voids
subtracted. Native refill (RATSNEST) and native DRC decide; the prediction is only for planning and reporting.

What is precomputed vs drawn live: all geometry is computed offline in this workspace; the recorded take draws the
accepted candidate net by net with raw EAGLE WIRE/VIA/POLYGON commands through fusion_electron_run, refills natively,
and runs fusion_routing_drc on the live board.