# BQ25792 board: independent electrical review and load contract (Fable 5 thread)

Status: DRAFT written before routing results; sections marked (measured) are filled from actual results.

## Source
- Board: adom/bq25792-charger, wiki commit 8e0f883e41cf327e9d33206be028c685a69cce40, package 0.1.85, Fusion v222.
- BRD sha256 f560054f4a71ad0f829261fd65ac665f87604b7d0fb9ccfcaddac648475bfb19 (shared-container copy == wiki clone).
- Schematic: bq25792-charger.sch from the same commit. BOM CSV carries footprints only (no values); values below come from the schematic part attributes.

## Topology as read from the schematic/PCB net membership (not from the wiki overview)
- Two DC inputs: VIN1 (J1) -> R2 0.01 ohm -> VAC1 -> Q1/Q2 (CSD17581Q3A back-to-back, sources tied = SRCTOSRC, gates N$2 driven from ACDRV1 via JP1/R4 294 ohm, D2 BZT52C12 gate clamp, C2 1 nF) -> VBUS.
  Input 2 is the mirror: VIN2 (J2) -> R6 -> VAC2 -> Q3/Q4 (SRCTOSRC1, gate N$34 from ACDRV2 via JP2/R9, D6, C4) -> VBUS.
  USB-C connector U$2 carries only power pins here (VUSB, PGND); JP7 (3x1) selects whether VUSB feeds VAC1 or VAC2. JP3/JP4 are bypass jumpers VBUS-VAC1 / VBUS-VAC2. VAC1/VAC2 are also sensed at IC1 pins 9/8 (C15/C14 0.1 uF to AGND).
- VBUS: IC1 pins 2,3; C11-C13 3x10 uF to PGND; D11 (BAT54) ORs VBUS into N$10.
- PMID: IC1 pin 29; C29-C31 3x10 uF + C32 0.1 uF; R5 0.01 ohm -> N$6 -> J4/TP17 (PMID/OTG output jumper).
- Switch nodes: SW1 (pin 28) and SW2 (pin 26) to inductor L2 FXL0530-100-M; bootstrap C6 (BTST1-SW1), C8 (BTST2-SW2).
- SYS: pin 25; C18 0.1 uF + C19-C23 5x10 uF; R3 0.01 ohm -> N$12 -> J3/TP16 (system load jumper).
- BAT: pins 22,23; C38/C39 10 uF; D12 ORs BAT into N$10; Q5 (CSD17581Q3A) source. Q5 gate = SDRV (pin 24, ship-FET driver), drain = VBAT -> XT60 (U$1), barrel jack nest (U$3), machine pin MP3, and R15 100 ohm -> BATP (pin 18, C1 47 nF).
  So Q5 is the external battery/ship FET; BATP senses the pack after it.
- Grounds: PGND (47 pads: IC1 pin 27, all bulk caps, connectors, EEPROM, LDO, pull-downs). AGND: C14, C15, R23, PRG, tied to PGND only through NT1 (2x1 jumper acting as a net tie). Keep AGND a separate quiet island joined at NT1.
- REGN (pin 5): C35 4.7 uF, R21 127k -> ILIM_HIZ (R23 100k to AGND), R14 5.1k -> TS (R16 5.1k to PGND). PROG via PRG (3x1) to AGND.
- Logic: SDA/SCL (pins 15/14) to U1 CAT24C256 EEPROM and machine pins MP7/MP8/MP11/MP12, 10k pull-ups R17/R18 to LDO_3V3; /INT MP9 + R19; /CE MP6 + R20 + JP5 (button SW1 via N$15); /QON MP5; STAT -> D1 red LED -> N$5 -> R1 2.2k -> LDO_3V3.
- D+/D- (pins 6/7) go only to machine pins MP14/MP13 (BC1.2 detection lines; not a high-speed USB pair on this board).
- 3.3 V: N$10 (ORed VBUS/BAT) -> R12 10 ohm 0.25 W -> N$14 (C43) -> U2 TLV76033 -> LDO_3V3 (C5, C3, U1, pull-ups, D3 white LED via N$16/R13 1k).
- EEPROM address/WP pins N$4/N$7/N$8/N$13 pulled to PGND by R10/R8/R7/R11 10k.

## Load contract (PROVISIONAL, not supplied by John; asked for in the report)
No operating currents were supplied. Component maximum ratings are not the load. Assumptions used for width/pour sizing, all labeled provisional:
- Charge current 3 A (BQ25792 programmable up to 5 A). Input current up to 3.3 A (device input limit). SYS load up to 3 A.
- Inductor current = up to charge current + ripple (~3.5-4 A peak in buck, higher in boost). SW1/SW2 carry it.
- Battery path (BAT, Q5, VBAT) up to 5 A discharge if the system draws through the pack; XT60 nest rated 20.8 A is a connector rating, not the load.
- 3.3 V rail: tens of mA (EEPROM + pull-ups + two LEDs).
- Gate nets, feedback (BATP, TS, ILIM_HIZ, PROG, REGN) and logic: signal level.
Design targets derived from these: power nets carried by pours where possible; traces >= 1.0 mm where pours cannot reach; IC pin escapes 0.2 mm (pad width) for the shortest possible length; signals 0.2 mm; clearances per inherited rules (0.1 mm copper, 0.15 mm pad-pad, 0.2 mm to board edge, drill spacing 0.2 mm). John's 0.1 mm ablation isolation floor is not smaller than any inherited rule, so the inherited rules govern.

## Thermal inventory (before allocating routes)
- IC1 BQ25792 RQM: the footprint used here has NO exposed-pad copper (33 perimeter SMD pads only); heat leaves through the power pins 25-29 (SYS, SW2, PGND, SW1, PMID) and pins 2/3 (VBUS), 22/23 (BAT). Estimated loss at 3 A/12 V in: ~1.5-2 W (efficiency ~93-95 %, provisional). Spreading copper must hang off these pins: SYS, PGND, VBUS, PMID, BAT. SW1/SW2 are high-dv/dt nodes and are kept compact.
- L2 FXL0530-100-M: DCR loss ~0.1-0.3 W at 3 A (provisional); its two 2.5 x 2.4 mm pads are SW1/SW2 (switching nodes), so no large pour extension on them.
- Q1-Q5 CSD17581Q3A: each has a drain tab (custom polygonshape pad on L1) plus 7 x 0.2 mm plated thermal holes inside the tab. Tab nets: Q1 VAC1, Q2 VBUS, Q4 VBUS, Q3 VAC2, Q5 VBAT (NOT ground). Losses ~40-100 mW each at 3-5 A (4 mohm class). Bottom-side pours on VAC1/VBUS/VAC2/VBAT under the tabs use the existing thermal holes.
- R2/R3/R5/R6 0.01 ohm 2010: 90 mW at 3 A, 250 mW at 5 A each. Their pads sit in the power pours.
- U2 TLV76033 + R12: negligible (tens of mW).
Existing thermal via arrays: none in the footprints besides the MOSFET thermal holes; the reference's vias under IC1 were signal vias (SW1/SW2/PGND) and are removed with the strip.

## Sensitive-signal constraints applied
- BATP (pin 18 <- R15/C1): short, away from SW nodes. TS, ILIM_HIZ, PROG, REGN divider: short, referenced to AGND/PGND per schematic.
- Gate drives N$2/N$34 and SDRV: moderate width (0.25 mm), kept short; the D2/D6 clamps are local.
- D+/D-: routed as a pair with a continuous ground reference (L2 PGND plane below).
- AGND island: joined to PGND only at NT1.

## Not qualified
A geometrically connected, DRC-clean board is not production qualified: no load, transient, EMI or thermal measurements were made. The load contract above is provisional.