# Independent BQ25792 Fusion routing experiment: report (Fable 5 thread)

(Skeleton; numbers filled at the end from measured files. Every number cites its source file.)

## Identity
- Provider/model: Anthropic, claude-fable-5-1 (Claude Fable 5.1), verified from the session transcript (`"model":"claude-fable-5-1"` on assistant messages after John switched the tab with /model; the first part of the session ran on claude-opus-5 and was stopped before any board work). Reasoning setting: CLAUDE_EFFORT=high.
- Date: 2026-09-07. Machine: AdomLapper (bridge target hostname verified). Container hostname AdomLapper.
- Fusion: <version> (from Fusion360.exe on host). Adom Bridge 2.1.60; Fusion bridge 1.10.0-dev.routing.5 (dev-pinned, preserved); add-in 1.0.19 after restart.
- Caller name: "Fable 5 BQ25792 comparison". Workspace: /home/adom/project/fable5-bq25792, branch fable5/bq25792-independent.

## Source board
- wiki adom/bq25792-charger @ 8e0f883e41cf327e9d33206be028c685a69cce40 (package 0.1.85, Fusion v222).
- BRD sha256 f560054f4a71ad0f829261fd65ac665f87604b7d0fb9ccfcaddac648475bfb19 (shared-container copy, wiki clone and host-staged copy all identical).
- Sanity: 109 elements, 50 nets, 304 pads (216 SMD + 88 THT), copper layers 1/2/15/16, outline 50.4 x 26.4 mm. Reference has 587 routed segments + 3 airwires, 88 vias, 0 pours.

## Baselines (native Autodesk DRC via fusion_routing_drc)
| board | rules | errors | warnings | airwires | file |
|---|---|---|---|---|---|
| reference (untouched) | untouched | 1611 | 14 | 3 | drc/normalized-reference-untouched.json |
| reference (diag copy) | only "Same-net track spacing" disabled | 7 | 14 | 3 | drc/normalized-reference-samenet-off.json |
| stripped (native RIPUP) | untouched | 7 | 0 | 179 | drc/normalized-stripped-untouched.json |
The 7 residual errors are fixed-copper pad-to-pad clearances (R17/MP7 incl. signature 5,1,f10227fd41e0ab5d, R20/MP6, C32/C18, U1 vs R7/R8/R10/R11); they are present on the stripped board, so no routing can remove them without moving parts.

## Planner
Own grid A* (0.05 mm), 8 directions, bend and via penalties, exact-disk clearance masks, same-net 0.25 mm spacing, escape stubs, dog-bone vias; no Freerouting/Fusion autorouter/fusion_plan_route. Iterations: v1..vN (planner/out/route-v*.log, all preserved).

## Results (measured)
## Routes-only candidate (route-v12z), measured
- Segments 846 (by layer: {1: 591, 2: 62, 15: 111, 16: 82}); total centreline length 1025.4 mm; widths {0.15: 245, 0.2: 146, 0.25: 90, 0.3: 125, 0.4: 12, 0.5: 93, 0.6: 31, 1.0: 104}.
- Segment kinds: {'stub': 69, 'route': 451, 'snap': 326} (stubs = pin escapes; joiners = corner-duplicate pad joins; snap = Fusion connectivity conformance pieces).
- Vias 73: {(0.4, 0.2): 46, (0.6, 0.3): 27} (0.4/0.2 signal class, 0.6/0.3 power class), by net {'!INT': 1, 'ILIM_HIZ': 2, 'ACDRV2': 2, '!CE': 2, 'SDA': 3, 'STAT': 2, 'REGN': 2, 'VAC1': 3, 'VAC2': 2, 'VBAT': 1, 'VIN1': 1, 'N$2': 2, 'N$3': 1, 'N$1': 2, 'N$15': 2, 'D_N': 3, 'PROG': 1, 'D_P': 4, 'SW1': 3, 'SW2': 3, 'PMID': 2, 'VBUS': 2, 'BAT': 3, 'PGND': 8, 'N$12': 2, 'LDO_3V3': 10, 'BATP': 2, 'SDRV': 2}.
- Off-angle segments: 0 (numeric audit, planner/out/route-v12z-check.json). Board-edge violations: 0.
- Exact-geometry check: 0 split nets, 1 clearance violation = inherited pad-pad R17.1/MP7 (0.128 < 0.15 mm).
- Native Fusion (fusion_routing_state after RATSNEST): 846 segments, 73 vias, airwires 0, remaining nets none.
- Native DRC, untouched rules: {'Wire Stub (type 1)': 83, 'Overlap (type 2)': 2290, 'Copper Clearance (type 2)': 442} -> the Same-net track spacing rule again dominates.
- Native DRC, diagnostic copy with ONLY 'Same-net track spacing' disabled: {'Wire Stub (type 1)': 83, 'Copper Clearance (type 2)': 1}; the single error is the inherited signature at (23.214, 1.914) on layer 1. Wire Stub warnings are dangling ends of snap/extension pieces (cosmetic; the reference had 14).
- Files: checkpoints/cand-v12z-routes.brd, checkpoints/cand-v12z-routes-native-export.brd (Fusion re-export), drc/candidate-v12z-routes-*.json.

(to fill) routing completion, segments, vias, pours, off-angle count, DRC errors/warnings/unconnected on candidate and on the recorded replay, copper areas by layer and per net, thermal comparison, finish decision, elapsed times, retry counts.


## Copper areas (union, drill-subtracted, mm^2; board 1330.56 mm^2)
| layer | fixed copper only (stripped) | reference (traces+pads) | candidate |
|---|---|---|---|
| L1 | 215.89 (16.23%) | 386.17 (29.02%) | (to fill) |
| L2 | 48.94 (3.68%) | 253.29 (19.04%) | (to fill) |
| L15 | 48.94 (3.68%) | 164.84 (12.39%) | (to fill) |
| L16 | 48.94 (3.68%) | 177.13 (13.31%) | (to fill) |


## Final candidate cand5 (routes + pours + expansion + island vias), measured
- Segments 866, vias 94 (21 stitching/island vias), pours 18; off-angle 0; exact check: 0 split nets, 1 inherited pad-pad violation.
- Native Fusion after RATSNEST: airwires 0, remaining nets none (drc/candidate-cand5-final-validation.json).
- Native DRC untouched rules: Overlap 2408, Copper Clearance 542 (both the inherited Same-net rule), Wire Stub warnings 83, 'Clearance (polygons with same rank)' 7.
- Native DRC diagnostic copy (only Same-net track spacing disabled): 1 Copper Clearance = inherited signature (23.214,1.914); 7 'Clearance (polygons with same rank)' = pour-outline proximity between my power pours near the FET tabs and the PMID/VBUS boundary (unresolved, listed in drc/candidate-cand5-final-samenet-off-drc-normalized.json); 83 Wire Stub warnings.

### Copper coverage by layer (mm^2, % of 1330.56)
| layer | stripped fixed copper | reference | candidate predicted (union, drill-subtracted) | candidate native image (cand3 geometry) |
|---|---|---|---|---|
| L1 | 215.89 (16.23%) | 386.17 (29.02%) | 943.06 (70.88%) | 910.5 (68.4%) |
| L2 | 48.94 (3.68%) | 253.29 (19.04%) | 1184.26 (89.0%) | 1168.5 (87.8%) |
| L15 | 48.94 (3.68%) | 164.84 (12.39%) | 1092.4 (82.1%) | 1048.7 (78.8%) |
| L16 | 48.94 (3.68%) | 177.13 (13.31%) | 1052.27 (79.08%) | 1033.3 (77.7%) |

### Connected pour area per net (mm^2, predicted from the same fill model that matched native images within ~3 %)
| net | layer | initial | after expansion/island vias |
|---|---|---|---|
| VBUS | L16 | 123.78 | 123.78 (islands 7.23) |
| VBUS | L1 | 96.78 | 96.78 (islands 12.47) |
| VAC1 | L16 | 81.17 | 109.36 (islands 0.0) |
| VAC1 | L1 | 79.46 | 107.13 (islands 1.26) |
| BAT | L16 | 11.84 | 17.83 (islands 10.35) |
| BAT | L1 | 8.36 | 11.86 (islands 4.63) |
| VAC2 | L16 | 95.1 | 121.26 (islands 0.51) |
| VAC2 | L1 | 68.39 | 82.28 (islands 6.59) |
| PMID | L16 | 29.12 | 38.07 (islands 26.17) |
| PMID | L1 | 25.24 | 42.2 (islands 14.45) |
| VBAT | L16 | 148.19 | 148.19 (islands 3.57) |
| VBAT | L1 | 25.76 | 25.76 (islands 0.0) |
| SYS | L16 | 48.36 | 16.4 (islands 32.63) |
| SYS | L1 | 30.95 | 31.02 (islands 6.04) |
| PGND | L2 | 1135.36 | 1136.15 (islands 0.38) |
| PGND | L15 | 949.13 | 949.92 (islands 15.82) |
| PGND | L16 | 369.76 | 345.27 (islands 49.24) |
| PGND | L1 | 358.06 | 324.75 (islands 74.17) |

Ground copper reassigned: PGND L16 connected fell from 369.76 to 345.27 mm^2 and L1 from 358.06 to 324.75 mm^2 between the initial pours and the final allocation; that area now belongs to VAC1/VAC2/BAT/PMID pours.

## Thermal comparison and finish decision
See docs/thermal-comparison.md (numbers from thermal/results-cand3.json, model thermal/plate_model.py). Decision: keep the solder mask; bare ENIG/HASL would lower the calculated exposed-face dissipation because of its low emissivity.

## Planner iteration history
See docs/planner-iterations.md (v1-v18 plus the finalizer/snap/closer stages; every log preserved under planner/out/). Retry counts: 18 full planner runs (5 stopped early), 3 finalizer runs, 5 snap/closer/viafix passes, 6 assemblies (cand0-cand5), 7 native validations of candidates.


## Effort (actual, from logs/timeline.log; UTC)
- Session start after the model switch: 2026-09-07 12:35. Verification, bridge discovery, parser and baselines: 12:35 to 13:16 (0.7 h).
- Planner development and iteration (v1-v18, finalizer, snap, closer, via fixes): 13:16 to about 00:30 next day (11.3 h including native validations of 7 candidates and 6 pour assemblies).
- Recorded takes: take 1 00:37 (1407 s wall, 5 residual airwires on the live board), take 2 with the in-take repair pass afterwards.
- Total wall time to the end of take 2 and postproduction: about 13 h, of which a large share was waiting on planner runs, native DRC and encoding. No token/cost data is available to me for this session.
- Fusion: 2705.1.11 (Fusion360.exe on AdomLapper); Adom Bridge 2.1.60; Fusion bridge 1.10.0-dev.routing.5 (dev-pinned, preserved); add-in restarted once to load the bundled 1.0.19.


## Recorded replay (take 2), measured on the live board
- Take 1 (00:36-01:00 UTC, preserved: video/raw/take-20260908T003647Z) ended with 5 native airwires because wires drawn live into pad origins were truncated at the pad boundary by Fusion's WIRE command; it is kept as evidence, not delivered as the demo.
- Take 2 (01:04-01:29 UTC): reference tour -> strip (0 segments, 0 vias, 194 airwires) -> 50 nets drawn live in 1014 s (876 segments, 94 vias, 9 airwires) -> in-take repair pass driven by Fusion's own airwire list (12 axis-aligned joiners; 3 airwires left, longer than the 2 mm joiner limit) -> initial pours -> expansion pours -> native SHOW highlights -> native DRC. Final live state: 888 segments, 94 vias, airwires 0, remaining nets none (logs/take2-final-state.json); the pours closed the last three airwires.
- Live DRC, untouched rules (drc/drc-take-live.json): Overlap 2522, Copper Clearance 633 (both dominated by the inherited Same-net rule), 'Clearance (polygons with same rank)' 12, Wire Stub warnings 127, airwires 0.
- Live DRC, diagnostic copy with only the Same-net rule disabled: see drc/drc-take-live-samenet-off-drc-normalized.json (filled below when the run completes).
- Live DRC, diagnostic copy (only Same-net rule disabled), replay: 65 Copper Clearance + 12 'polygons with same rank' + 127 Wire Stub warnings (drc/drc-take-live-samenet-off-drc-normalized.json), versus 1 + 7 + 83 on the injected candidate. Cause found after the take: the live VIA command takes only the diameter and the take issued one CHANGE DRILL 0.3 for all vias, so the 46 signal vias meant to be 0.4/0.2 mm were created with a 0.3 mm drill and grew to 0.5 mm outer; neighbouring signal vias (ACDRV2/D_N, !CE/LDO_3V3, D_P/ILIM_HIZ, ...) then sit inside each other's 0.1 mm clearance and are reported once per copper layer. The injected candidate has the correct drills. planner/emit.py now emits CHANGE DRILL per via; there was no time for a third take, so the video shows the 0.5 mm signal vias and its DRC numbers are reported as they are.
- Native exports of the replayed board: checkpoints/take2-final-native.fbrd (Fusion) and take2-final-native-export.brd (EAGLE XML); delivered as evidence/take-final-native.fbrd / .brd.

## Deliverables (on AdomLapper)
Folder: C:/Users/john/Documents/Adom Routing Demos/fable5-bq25792-independent-2026-09-07/
- fable5-bq25792-independent-narrated.mp4 (671.8 s, 1920x1080 H.264 + AAC, faststart, 49 MB; full decode checked, 20155 frames, contact sheet logs/final-output-sheet.png, peak -0.8 dBFS, mean -19 dB). Opened in the host Media Player and screenshotted (screenshots/adom-bridge/window/2026-09-08T01-36-59.729-24189966.safe.png).
- README.md, evidence/ (30 files): native FBRD + readable BRD of the recorded replay, the validated candidate BRD, planner JSONs, normalized native DRC results for every stage, the take's call log with UTC timestamps, edit manifest, silent captioned cut, thermal results, native copper areas, timeline, and these documents.
- Container workspace (branch fable5/bq25792-independent): /home/adom/project/fable5-bq25792 with planner source, every planner log (planner/out), both raw recordings (video/raw, 1.87 GB and 1.96 GB), checkpoints and DRC JSONs.
Known presentation limits: two captions are longer than the frame width and are clipped at the edges (pours and the final path caption); the video shows the 0.5 mm signal vias explained above.

## Addendum 2026-09-08: side-by-side net comparison video
- fable5-vs-adonis-net-by-net.mp4 (128 s, 1920x1080 H.264/AAC): two native Fusion window recordings (untouched reference adonis-reference.brd and my validated cand5 board fable5-routed.brd, both file-opened, all copper layers displayed, WINDOW FIT, same scale), each cycling `SHOW <net>` over all 50 nets in the same family order (1.6 s dwell, timestamps in evidence/compare-show-log-*.jsonl). For every net the frame with the strongest native highlight inside its dwell window is cropped to the board canvas and composited left (Adonis) / right (mine) with one fact line per side from evidence/compare-net-facts.json (segments, length, width range, layers, vias, pours, airwires). 2.0 s per net, 13 s intro, 15 s outro; narration (Adom TTS, nine beats by net family) explains the reasoning: input path on pours through the FET tab holes vs 1.27 mm traces, compact switch nodes with 3 vs 8 vias, bottom pours as the heatsink for a chip without a thermal pad, an L2 ground plane vs 45 top traces, 0.15 mm QFN escapes with dog-bone vias, inner-layer D+/D-, and the unfinished LDO_3V3 airwires on the reference. The composite is labelled as postproduction on screen; the highlights themselves are native.