DS90UB934TRGZRQ1

{
  "slug": "ds90ub934trgzrq1",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments LVDS ICs, VQFN-48-EP(7x7). Datasheet-verified pinout, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "interface",
    "ds90ub934trgzrq1",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "ds90ub934trgzrq1.kicad_sym",
    "ds90ub934trgzrq1.kicad_mod",
    "ds90ub934trgzrq1.glb",
    "ds90ub934trgzrq1.step",
    "ds90ub934trgzrq1.lbr",
    "docs/hero.png",
    "docs/ds90ub934trgzrq1-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html"
  ],
  "component": {
    "mpn": "DS90UB934TRGZRQ1",
    "manufacturer": "Texas Instruments",
    "package": "VQFN-48-EP(7x7)",
    "pin_count": 49,
    "category": "Interface",
    "subcategory": "LVDS ICs",
    "datasheet": "https://www.ti.com/cn/lit/gpn/ds90ub934-q1",
    "parts": {
      "symbol": "ds90ub934trgzrq1.kicad_sym",
      "footprint": "ds90ub934trgzrq1.kicad_mod",
      "model_3d": "ds90ub934trgzrq1-etched.glb",
      "model_3d_plain": "ds90ub934trgzrq1.glb",
      "model_3d_step": "ds90ub934trgzrq1-etched.step",
      "model_3d_step_plain": "ds90ub934trgzrq1.step",
      "lbr": "ds90ub934trgzrq1.lbr"
    },
    "distributor_links": {
      "lcsc": "C2927520"
    },
    "pins": [
      {
        "number": "1",
        "name": "I2C_SDA",
        "type": "bidirectional",
        "description": "I2C serial data line for bidirectional control bus communication with external 2-kΩ to 4.7-kΩ pullup resistor to VI2C recommended."
      },
      {
        "number": "2",
        "name": "I2C_SCL",
        "type": "bidirectional",
        "description": "I2C serial clock line for bidirectional control bus communication with external 2-kΩ to 4.7-kΩ pullup resistor to VI2C recommended."
      },
      {
        "number": "3",
        "name": "VDD11_D",
        "type": "passive",
        "description": "Decoupling capacitor connection for internal digital regulator, requires minimum 4.7-μF capacitor to GND."
      },
      {
        "number": "4",
        "name": "OSS_SEL",
        "type": "input",
        "description": "Output sleep state select pin with 25-kΩ internal pulldown; if unused connect to VDD with ≤4.3-kΩ pullup resistor."
      },
      {
        "number": "5",
        "name": "OEN",
        "type": "input",
        "description": "Output enable pin with 1-MΩ internal pulldown; if unused connect to VDD with ≤4.3-kΩ pullup resistor."
      },
      {
        "number": "6",
        "name": "BISTEN",
        "type": "input",
        "description": "BIST enable pin with 25-kΩ internal pulldown; when HIGH enables BIST mode for at-speed testing."
      },
      {
        "number": "7",
        "name": "VDDIO",
        "type": "power_in",
        "description": "VDDIO voltage supply input for single-ended outputs and control inputs, 1.8V ±5% or 3.0-3.6V with minimum 10-nF capacitor to GND."
      },
      {
        "number": "8",
        "name": "PCLK",
        "type": "output",
        "description": "Pixel clock output at VDDIO logic levels, frequency range 25-100 MHz depending on mode."
      },
      {
        "number": "9",
        "name": "VSYNC",
        "type": "output",
        "description": "Vertical SYNC output at VDDIO logic levels from FPD-LINK III deserializer."
      },
      {
        "number": "10",
        "name": "HSYNC",
        "type": "output",
        "description": "Horizontal SYNC output at VDDIO logic levels from FPD-LINK III deserializer."
      },
      {
        "number": "11",
        "name": "ROUT11",
        "type": "output",
        "description": "Receive data output bit 11 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels."
      },
      {
        "number": "12",
        "name": "ROUT10",
        "type": "output",
        "description": "Receive data output bit 10 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels."
      },
      {
        "number": "13",
        "name": "ROUT9",
        "type": "output",
        "description": "Receive data output bit 9 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels."
      },
      {
        "number": "14",
        "name": "ROUT8",
        "type": "output",
        "description": "Receive data output bit 8 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels."
      },
      {
        "number": "15",
        "name": "ROUT7",
        "type": "output",
        "description": "Receive data output bit 7 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels."
      },
      {
        "number": "16",
        "name": "ROUT6",
        "type": "output",
        "description": "Receive data output bit 6 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels."
      },
      {
        "number": "17",
        "name": "VDD18",
        "type": "power_in",
        "description": "1.8V ±5% power supply requiring 1-μF, 0.1-μF, and 0.01-μF capacitors to GND at each VDD pin."
      },
      {
        "number": "18",
        "name": "ROUT5",
        "type": "output",
        "description": "Receive data output bit 5 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels."
      },
      {
        "number": "19",
        "name": "ROUT4",
        "type": "output",
        "description": "Receive data output bit 4 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels."
      },
      {
        "number": "20",
        "name": "VDD11_DVP",
        "type": "passive",
        "description": "Decoupling capacitor connection for internal mixed signal regulator, requires minimum 4.7-μF capacitor to GND."
      },
      {
        "number": "21",
        "name": "ROUT3",
        "type": "output",
        "description": "Receive data output bit 3 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels."
      },
      {
        "number": "22",
        "name": "ROUT2",
        "type": "output",
        "description": "Receive data output bit 2 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels."
      },
      {
        "number": "23",
        "name": "ROUT1",
        "type": "output",
        "description": "Receive data output bit 1 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels."
      },
      {
        "number": "24",
        "name": "ROUT0",
        "type": "output",
        "description": "Receive data output bit 0 of parallel CMOS interface from FPD-LINK III deserializer, configurable for 10 or 12-bit at VDDIO logic levels."
      },
      {
        "number": "25",
        "name": "GPIO3/INTB",
        "type": "bidirectional",
        "description": "General purpose input/output or active-low open drain interrupt output, shared pin with pullup to VI2C required at 4.7 kΩ."
      },
      {
        "number": "26",
        "name": "GPIO2",
        "type": "bidirectional",
        "description": "General purpose input/output with 25-kΩ pulldown; unused pins may be left open or floating at VDDIO logic levels."
      },
      {
        "number": "27",
        "name": "GPIO1",
        "type": "bidirectional",
        "description": "General purpose input/output with 25-kΩ pulldown; unused pins may be left open or floating at VDDIO logic levels."
      },
      {
        "number": "28",
        "name": "GPIO0",
        "type": "bidirectional",
        "description": "General purpose input/output with 25-kΩ pulldown; unused pins may be left open or floating at VDDIO logic levels."
      },
      {
        "number": "29",
        "name": "VDDIO",
        "type": "power_in",
        "description": "VDDIO voltage supply input for single-ended outputs and control inputs, 1.8V ±5% or 3.0-3.6V with minimum 10-nF capacitor to GND."
      },
      {
        "number": "30",
        "name": "PDB",
        "type": "input",
        "description": "Power-down inverted input pin with 50-kΩ internal pulldown and 3.3V tolerance; HIGH enables device, LOW powers down."
      },
      {
        "number": "31",
        "name": "VDD18_FPD1",
        "type": "power_in",
        "description": "1.8V ±5% high-speed transceiver analog power supply requiring 10-μF, 0.1-μF, and 0.01-μF capacitors to GND."
      },
      {
        "number": "32",
        "name": "RIN1+",
        "type": "bidirectional",
        "description": "Receive input channel 1 positive differential FPD-Link receiver with bidirectional control back channel and internal 100-Ω termination."
      },
      {
        "number": "33",
        "name": "RIN1-",
        "type": "bidirectional",
        "description": "Receive input channel 1 negative differential FPD-Link receiver with internal 100-Ω termination to RIN1+, AC-coupled input required."
      },
      {
        "number": "34",
        "name": "VDD11_FPD",
        "type": "passive",
        "description": "Decoupling capacitor connection for internal analog regulator, requires minimum 4.7-μF capacitor to GND."
      },
      {
        "number": "35",
        "name": "IDX",
        "type": "input",
        "description": "I2C device ID address input via voltage divider with external pullup to VDD18 and pulldown to GND for 8 possible addresses."
      },
      {
        "number": "36",
        "name": "VDD18_P1",
        "type": "power_in",
        "description": "1.8V ±5% PLL power supply requiring 1-μF, 0.1-μF, and 0.01-μF capacitors to GND."
      },
      {
        "number": "37",
        "name": "MODE",
        "type": "input",
        "description": "Mode select configuration input via voltage divider to VDD18 and GND for selecting COAX/STP and operating mode (RAW12 HF/LF or RAW10)."
      },
      {
        "number": "38",
        "name": "CMLOUTP",
        "type": "output",
        "description": "Channel monitor loop-through CML driver differential output positive for observing jitter after equalization."
      },
      {
        "number": "39",
        "name": "CMLOUTN",
        "type": "output",
        "description": "Channel monitor loop-through CML driver differential output negative with 100-Ω differential load termination."
      },
      {
        "number": "40",
        "name": "VDD18_FPD0",
        "type": "power_in",
        "description": "1.8V ±5% high-speed transceiver analog power supply requiring 10-μF, 0.1-μF, and 0.01-μF capacitors to GND."
      },
      {
        "number": "41",
        "name": "RIN0+",
        "type": "bidirectional",
        "description": "Receive input channel 0 positive differential FPD-Link receiver with bidirectional control back channel and internal 100-Ω termination."
      },
      {
        "number": "42",
        "name": "RIN0-",
        "type": "bidirectional",
        "description": "Receive input channel 0 negative differential FPD-Link receiver with internal 100-Ω termination to RIN0+, AC-coupled input required."
      },
      {
        "number": "43",
        "name": "RES",
        "type": "unconnected",
        "description": "Reserved pin with internal pull-up resistor, must be tied to GND for normal operation."
      },
      {
        "number": "44",
        "name": "RES",
        "type": "unconnected",
        "description": "Reserved pin, must be NC or tied to GND for normal operation."
      },
      {
        "number": "45",
        "name": "VDD18_P0",
        "type": "power_in",
        "description": "1.8V ±5% PLL power supply requiring 1-μF, 0.1-μF, and 0.01-μF capacitors to GND."
      },
      {
        "number": "46",
        "name": "SEL",
        "type": "input",
        "description": "MUX select digital input with 25-kΩ internal pulldown for selecting FPD Link input channel 0 or 1 at VDDIO logic levels."
      },
      {
        "number": "47",
        "name": "PASS",
        "type": "output",
        "description": "PASS output HIGH for error-free transmission in forward channel, LOW indicates one or more errors detected at VDDIO logic levels."
      },
      {
        "number": "48",
        "name": "LOCK",
        "type": "output",
        "description": "LOCK status output HIGH when PLL is locked and outputs active, LOW when unlocked at VDDIO logic levels."
      },
      {
        "number": "49",
        "name": "EP",
        "type": "passive",
        "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.2",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.2",
        "primary_model": "claude-haiku-4-5-20251001",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-4-6",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Thermal pad DAP located at package center and connected to GND; not a numbered pin in standard count",
          "exposed pad 49 added from the footprint"
        ],
        "pages_sent": 84,
        "cost_usd": 0.9193,
        "at": "2026-09-22T07:26:30"
      },
      "datasheet": {
        "url": "https://www.ti.com/cn/lit/gpn/ds90ub934-q1",
        "pages": 84,
        "sha256": "c545e4c689385e29",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 49,
        "described": 49,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "ds90ub934trgzrq1.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          7.0,
          7.0,
          0.77
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "f2b38b0b4bf967c77e683e8d4599608b9f0503055ec535b93c4ebb5d0163e916",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "ds90ub934trgzrq1-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          7.0,
          7.0,
          0.77
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "d68fb187ef9d9aaaa34c77f6a494e1a54a3499e99a03478ebab0de0e815afc58",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}