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DS90UB934TRGZRQ1

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Texas Instruments LVDS ICs, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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DS90UB934TRGZRQ1

Texas Instruments · LVDS ICs · VQFN-48-EP(7x7)

DS90UB934TRGZRQ1 from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 I2C_SDA bidirectional I2C serial data line for bidirectional control bus communication with external 2-kΩ to 4.7-kΩ pullup resistor to VI2C recommended.
2 I2C_SCL bidirectional I2C serial clock line for bidirectional control bus communication with external 2-kΩ to 4.7-kΩ pullup resistor to VI2C recommended.
3 VDD11_D passive Decoupling capacitor connection for internal digital regulator, requires minimum 4.7-μF capacitor to GND.
4 OSS_SEL input Output sleep state select pin with 25-kΩ internal pulldown; if unused connect to VDD with ≤4.3-kΩ pullup resistor.
5 OEN input Output enable pin with 1-MΩ internal pulldown; if unused connect to VDD with ≤4.3-kΩ pullup resistor.
6 BISTEN input BIST enable pin with 25-kΩ internal pulldown; when HIGH enables BIST mode for at-speed testing.
7 VDDIO power_in VDDIO voltage supply input for single-ended outputs and control inputs, 1.8V ±5% or 3.0-3.6V with minimum 10-nF capacitor to GND.
8 PCLK output Pixel clock output at VDDIO logic levels, frequency range 25-100 MHz depending on mode.
9 VSYNC output Vertical SYNC output at VDDIO logic levels from FPD-LINK III deserializer.
10 HSYNC output Horizontal SYNC output at VDDIO logic levels from FPD-LINK III deserializer.
11 ROUT11 output Receive data output bit 11 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels.
12 ROUT10 output Receive data output bit 10 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels.
13 ROUT9 output Receive data output bit 9 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels.
14 ROUT8 output Receive data output bit 8 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels.
15 ROUT7 output Receive data output bit 7 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels.
16 ROUT6 output Receive data output bit 6 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels.
17 VDD18 power_in 1.8V ±5% power supply requiring 1-μF, 0.1-μF, and 0.01-μF capacitors to GND at each VDD pin.
18 ROUT5 output Receive data output bit 5 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels.
19 ROUT4 output Receive data output bit 4 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels.
20 VDD11_DVP passive Decoupling capacitor connection for internal mixed signal regulator, requires minimum 4.7-μF capacitor to GND.
21 ROUT3 output Receive data output bit 3 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels.
22 ROUT2 output Receive data output bit 2 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels.
23 ROUT1 output Receive data output bit 1 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels.
24 ROUT0 output Receive data output bit 0 of parallel CMOS interface from FPD-LINK III deserializer, configurable for 10 or 12-bit at VDDIO logic levels.
25 GPIO3/INTB bidirectional General purpose input/output or active-low open drain interrupt output, shared pin with pullup to VI2C required at 4.7 kΩ.
26 GPIO2 bidirectional General purpose input/output with 25-kΩ pulldown; unused pins may be left open or floating at VDDIO logic levels.
27 GPIO1 bidirectional General purpose input/output with 25-kΩ pulldown; unused pins may be left open or floating at VDDIO logic levels.
28 GPIO0 bidirectional General purpose input/output with 25-kΩ pulldown; unused pins may be left open or floating at VDDIO logic levels.
29 VDDIO power_in VDDIO voltage supply input for single-ended outputs and control inputs, 1.8V ±5% or 3.0-3.6V with minimum 10-nF capacitor to GND.
30 PDB input Power-down inverted input pin with 50-kΩ internal pulldown and 3.3V tolerance; HIGH enables device, LOW powers down.
31 VDD18_FPD1 power_in 1.8V ±5% high-speed transceiver analog power supply requiring 10-μF, 0.1-μF, and 0.01-μF capacitors to GND.
32 RIN1+ bidirectional Receive input channel 1 positive differential FPD-Link receiver with bidirectional control back channel and internal 100-Ω termination.
33 RIN1- bidirectional Receive input channel 1 negative differential FPD-Link receiver with internal 100-Ω termination to RIN1+, AC-coupled input required.
34 VDD11_FPD passive Decoupling capacitor connection for internal analog regulator, requires minimum 4.7-μF capacitor to GND.
35 IDX input I2C device ID address input via voltage divider with external pullup to VDD18 and pulldown to GND for 8 possible addresses.
36 VDD18_P1 power_in 1.8V ±5% PLL power supply requiring 1-μF, 0.1-μF, and 0.01-μF capacitors to GND.
37 MODE input Mode select configuration input via voltage divider to VDD18 and GND for selecting COAX/STP and operating mode (RAW12 HF/LF or RAW10).
38 CMLOUTP output Channel monitor loop-through CML driver differential output positive for observing jitter after equalization.
39 CMLOUTN output Channel monitor loop-through CML driver differential output negative with 100-Ω differential load termination.
40 VDD18_FPD0 power_in 1.8V ±5% high-speed transceiver analog power supply requiring 10-μF, 0.1-μF, and 0.01-μF capacitors to GND.
41 RIN0+ bidirectional Receive input channel 0 positive differential FPD-Link receiver with bidirectional control back channel and internal 100-Ω termination.
42 RIN0- bidirectional Receive input channel 0 negative differential FPD-Link receiver with internal 100-Ω termination to RIN0+, AC-coupled input required.
43 RES unconnected Reserved pin with internal pull-up resistor, must be tied to GND for normal operation.
44 RES unconnected Reserved pin, must be NC or tied to GND for normal operation.
45 VDD18_P0 power_in 1.8V ±5% PLL power supply requiring 1-μF, 0.1-μF, and 0.01-μF capacitors to GND.
46 SEL input MUX select digital input with 25-kΩ internal pulldown for selecting FPD Link input channel 0 or 1 at VDDIO logic levels.
47 PASS output PASS output HIGH for error-free transmission in forward channel, LOW indicates one or more errors detected at VDDIO logic levels.
48 LOCK output LOCK status output HIGH when PLL is locked and outputs active, LOW when unlocked at VDDIO logic levels.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-48-EP(7x7)
Category Interface
Pins 49

CAD (KiCad official)

  • Symbol: DS90UB934TRGZRQ1
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: ds90ub934trgzrq1-etched.step / ds90ub934trgzrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds90ub934trgzrq1.step / ds90ub934trgzrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (84 pp, sha256 c545e4c689385e29, retrieved 2026-09-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF