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DRV8300DRGER

Public Made by Adom

by adom

Texas Instruments Gate Drivers, VQFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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docs drv8300drger: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers drv8300drger: viewers · Ray
drv8300drger-etched.fit.json drv8300drger: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
drv8300drger-etched.glb drv8300drger: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
drv8300drger-etched.step drv8300drger: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
drv8300drger.glb Publish 0.1.0 · Ray
drv8300drger.kicad_mod Publish 0.1.0 · Ray
drv8300drger.kicad_sym Publish 0.1.0 · Ray
drv8300drger.lbr Publish 0.1.0 · Ray
drv8300drger.step Publish 0.1.0 · Ray
package.json drv8300drger: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
page.json drv8300drger: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md Initial commit: component/drv8300drger · Ray

DRV8300DRGER

Texas Instruments · Gate Drivers · VQFN-24(4x4)

DRV8300DRGER from Texas Instruments, in a VQFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 INLA input Low-side gate driver control input for phase A; VIL ≤ 0.8 V, VIH ≥ 2.0 V; 120-280 kΩ pull-down to GND in non-inverting mode or pull-up to INT_5V in inverting mode.
2 INLB input Low-side gate driver control input for phase B; VIL ≤ 0.8 V, VIH ≥ 2.0 V; 120-280 kΩ pull-down to GND in non-inverting mode or pull-up to INT_5V in inverting mode.
3 INLC input Low-side gate driver control input for phase C; VIL ≤ 0.8 V, VIH ≥ 2.0 V; 120-280 kΩ pull-down to GND in non-inverting mode or pull-up to INT_5V in inverting mode.
4 GVDD power_in Gate driver power supply input; recommended operating range 5 V to 20 V; connect ≥10 µF X5R/X7R ceramic decoupling capacitor between GVDD and GND.
5 MODE input Mode input selects GLx output polarity: floating = non-inverted (GLx in phase with INLx), connected to GVDD = inverted; VIL ≤ 0.6 V, VIH ≥ 3.7 V; 120-280 kΩ pull-down to GND.
6 GND power_in Device ground.
7 NC unconnected No internal connection; may be left floating or connected to system ground.
8 NC unconnected No internal connection; may be left floating or connected to system ground.
9 GLC output Low-side gate driver output for phase C; connect to gate of low-side power MOSFET; peak source 750 mA, peak sink 1.5 A; voltage swings 0 V to VGVDD.
10 GLB output Low-side gate driver output for phase B; connect to gate of low-side power MOSFET; peak source 750 mA, peak sink 1.5 A; voltage swings 0 V to VGVDD.
11 GLA output Low-side gate driver output for phase A; connect to gate of low-side power MOSFET; peak source 750 mA, peak sink 1.5 A; voltage swings 0 V to VGVDD.
12 SHC passive High-side source sense input for phase C; connect to source of high-side power MOSFET (switch node); rated −2 V to 85 V DC, transient −22 V / 2 µs; leakage current ≤ 80 µA at VSHx = 0-85 V.
13 GHC output High-side gate driver output for phase C; connect to gate of high-side power MOSFET; peak source 750 mA, peak sink 1.5 A; absolute maximum 125 V; swings between SHC and BSTC.
14 BSTC output Bootstrap output for phase C; connect capacitor between BSTC and SHC (≥100 nF recommended); absolute maximum 125 V; DRV8300D uses integrated bootstrap diode from GVDD.
15 SHB passive High-side source sense input for phase B; connect to source of high-side power MOSFET (switch node); rated −2 V to 85 V DC, transient −22 V / 2 µs; leakage current ≤ 80 µA at VSHx = 0-85 V.
16 GHB output High-side gate driver output for phase B; connect to gate of high-side power MOSFET; peak source 750 mA, peak sink 1.5 A; absolute maximum 125 V; swings between SHB and BSTB.
17 BSTB output Bootstrap output for phase B; connect capacitor between BSTB and SHB (≥100 nF recommended); absolute maximum 125 V; DRV8300D uses integrated bootstrap diode from GVDD.
18 SHA passive High-side source sense input for phase A; connect to source of high-side power MOSFET (switch node); rated −2 V to 85 V DC, transient −22 V / 2 µs; leakage current ≤ 80 µA at VSHx = 0-85 V.
19 GHA output High-side gate driver output for phase A; connect to gate of high-side power MOSFET; peak source 750 mA, peak sink 1.5 A; absolute maximum 125 V; swings between SHA and BSTA.
20 BSTA output Bootstrap output for phase A; connect capacitor between BSTA and SHA (≥100 nF recommended); absolute maximum 125 V; DRV8300D uses integrated bootstrap diode from GVDD.
21 DT input Deadtime control input (QFN-24 only); connect resistor to GND for variable deadtime (200 ns to 2000 ns linearly adjustable); floating = 215 ns typical fixed deadtime.
22 INHA input High-side gate driver control input for phase A; VIL ≤ 0.8 V, VIH ≥ 2.0 V; 120-280 kΩ pull-down to GND.
23 INHB input High-side gate driver control input for phase B; VIL ≤ 0.8 V, VIH ≥ 2.0 V; 120-280 kΩ pull-down to GND.
24 INHC input High-side gate driver control input for phase C; VIL ≤ 0.8 V, VIH ≥ 2.0 V; 120-280 kΩ pull-down to GND.
25 PowerPAD power_in Exposed thermal pad; must be soldered to PCB thermal pad for thermal and mechanical performance; RθJC(bot) = 11.5 °C/W.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-24(4x4)
Category Motor Driver ICs
Pins 25

CAD (KiCad official)

  • Symbol: DRV8300DRGER
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm
  • 3D model: VQFN-24(4x4) (KiCad packages3D, STEP)
  • 3D model files: drv8300drger-etched.step / drv8300drger-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); drv8300drger.step / drv8300drger.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (35 pp, sha256 ce0cba4354bb3566, retrieved 2026-09-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF