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DMG6602SVT-7

Public Made by Adom

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Diodes Incorporated MOSFETs, TSOT-26. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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docs dmg6602svt-7: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers dmg6602svt-7: viewers · Ray
dmg6602svt-7-etched.fit.json dmg6602svt-7: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
dmg6602svt-7-etched.glb dmg6602svt-7: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
dmg6602svt-7-etched.step dmg6602svt-7: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
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package.json dmg6602svt-7: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
page.json dmg6602svt-7: specified limits as data (metadata.characteristics, 49 rows from the datasheet) · Ray
README.md dmg6602svt-7: specified limits as data (metadata.characteristics, 49 rows from the datasheet) · Ray

DMG6602SVT-7

Diodes Incorporated · MOSFETs · TSOT-26

DMG6602SVT-7 from Diodes Incorporated, in a TSOT-26. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 D1 passive Drain of Q1 N-channel MOSFET; VDSS = 30V, RDS(on) = 60mΩ (typ.) / 100mΩ (max) at VGS = 10V / 4.5V; continuous drain current ID = 3.4A at TA = +25°C.
2 S1 passive Source of Q1 N-channel MOSFET; body diode forward voltage VSD = 0.8V (typ.) / 1.0V (max) at IS = 1A; maximum continuous body diode forward current IS = 1.5A.
3 D2 passive Drain of Q2 P-channel MOSFET; VDSS = -30V, RDS(on) = 95mΩ (typ.) / 140mΩ (max) at VGS = -10V / -4.5V; continuous drain current ID = -2.8A at TA = +25°C.
4 G2 input Gate of Q2 P-channel MOSFET; gate threshold voltage VGS(th) = -1.0V to -2.3V at ID = -250μA; maximum gate-source voltage VGSS = ±20V.
5 S2 passive Source of Q2 P-channel MOSFET; body diode forward voltage VSD = -0.8V (typ.) / -1.0V (max) at IS = -1A; maximum continuous body diode forward current IS = -1.5A.
6 G1 input Gate of Q1 N-channel MOSFET; gate threshold voltage VGS(th) = 1.0V to 2.3V at ID = 250μA; maximum gate-source voltage VGSS = ±20V.

Key specifications

Parameter Value
Manufacturer Diodes Incorporated
Package TSOT-26
Category Transistors/Thyristors
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-Source Breakdown Voltage (Q1 NMOS) BVDSS 30 V VGS = 0V, ID = 250µA 3
Zero Gate Voltage Drain Current (Q1 NMOS) IDSS 1 µA VDS = 24V, VGS = 0V 3
Gate-Source Leakage (Q1 NMOS) IGSS -100 100 nA VGS = ±20V, VDS = 0V 3
Gate Threshold Voltage (Q1 NMOS) VGS(th) 1 2.3 V VDS = VGS, ID = 250μA 3
Static Drain-Source On-Resistance (Q1 NMOS) RDS(ON) 38 60 mΩ VGS = 10V, ID = 3.1A 3
Static Drain-Source On-Resistance (Q1 NMOS) RDS(ON) 55 100 mΩ VGS = 4.5V, ID = 2A 3
Diode Forward Voltage (Q1 NMOS) VSD 0.8 1 V VGS = 0V, IS = 1A 3
Input Capacitance (Q1 NMOS) Ciss 290 400 pF VDS = 15V, VGS = 0V, f = 1.2MHz 3
Output Capacitance (Q1 NMOS) Coss 40 80 pF VDS = 15V, VGS = 0V, f = 1.2MHz 3
Reverse Transfer Capacitance (Q1 NMOS) Crss 40 80 pF VDS = 15V, VGS = 0V, f = 1.2MHz 3
Total Gate Charge (Q1 NMOS, VGS = 4.5V) Qg 4 6 nC VDS = 15V, VGS = 4.5V, ID = 3.1A 3
Total Gate Charge (Q1 NMOS, VGS = 10V) Qg 9 13 nC 3
Drain-Source Breakdown Voltage (Q2 PMOS) BVDSS -30 V VGS = 0V, ID = -250µA 6
Zero Gate Voltage Drain Current (Q2 PMOS) IDSS -1 µA VDS = -24V, VGS = 0V 6
Gate-Source Leakage (Q2 PMOS) IGSS -100 100 nA VGS = ±20V, VDS = 0V 6
Gate Threshold Voltage (Q2 PMOS) VGS(th) -1 -2.3 V VDS = VGS, ID = -250μA 6
Static Drain-Source On-Resistance (Q2 PMOS) RDS(ON) 73 95 mΩ VGS = -10V, ID = -2.7A 6
Static Drain-Source On-Resistance (Q2 PMOS) RDS(ON) 99 140 mΩ VGS = -4.5V, ID = -2A 6
Diode Forward Voltage (Q2 PMOS) VSD -0.8 -1 V VGS = 0V, IS = -1A 6
Input Capacitance (Q2 PMOS) Ciss 350 420 pF VDS = -15V, VGS = 0V, f = 1.2MHz 6
Output Capacitance (Q2 PMOS) Coss 50 100 pF VDS = -15V, VGS = 0V, f = 1.2MHz 6
Reverse Transfer Capacitance (Q2 PMOS) Crss 45 80 pF VDS = -15V, VGS = 0V, f = 1.2MHz 6
Total Gate Charge (Q2 PMOS, VGS = -4.5V) Qg 4 6 nC VDS = -15V, VGS = -4.5V, ID = -3A 6
Total Gate Charge (Q2 PMOS, VGS = -10V) Qg 7 9 nC 6
Drain-Source Voltage (Q1 NMOS) VDSS 30 V TA = +25°C 2
Gate-Source Voltage (Q1 NMOS) VGSS -20 20 V 2
Continuous Drain Current (Q1 NMOS) ID 3.4 A VGS = 10V, steady state, TA = +25°C (note 6) 2
Continuous Drain Current (Q1 NMOS) ID 2.7 A VGS = 10V, steady state, TA = +70°C (note 6) 2
Continuous Drain Current (Q1 NMOS) ID 2.2 A VGS = 4.5V, steady state, TA = +70°C (note 6) 2
Maximum Continuous Body Diode Forward Current (Q1 NMOS) IS 1.5 A note 6 2
Pulsed Drain Current (Q1 NMOS) IDM 25 A note 6 2
Drain-Source Voltage (Q2 PMOS) VDSS -30 V TA = +25°C 2
Gate-Source Voltage (Q2 PMOS) VGSS -20 20 V 2
Continuous Drain Current (Q2 PMOS) ID -2.8 A VGS = -10V, steady state, TA = +25°C (note 6) 2
Continuous Drain Current (Q2 PMOS) ID -2.4 A VGS = -10V, steady state, TA = +70°C (note 6) 2
Continuous Drain Current (Q2 PMOS) ID -2.3 A VGS = -4.5V, steady state, TA = +25°C (note 6) 2
Continuous Drain Current (Q2 PMOS) ID -2.1 A VGS = -4.5V, steady state, TA = +70°C (note 6) 2
Maximum Continuous Body Diode Forward Current (Q2 PMOS) IS -1.5 A note 6 2
Pulsed Drain Current (Q2 PMOS) ID -20 A Pulsed, note 6 2
Operating and Storage Temperature Range TJ, TSTG -55 150 °C 2
Total Power Dissipation PD 0.84 W TA = +25°C, note 5 (minimum pad layout) 2
Total Power Dissipation PD 0.52 W TA = +70°C, note 5 (minimum pad layout) 2
Total Power Dissipation PD 1.27 W TA = +25°C, note 6 (1 inch square copper plate) 2
Total Power Dissipation PD 0.8 W TA = +70°C, note 6 (1 inch square copper plate) 2
Thermal Resistance, Junction to Ambient RϴJA 155 °C/W Steady state, note 5 2
Thermal Resistance, Junction to Ambient RϴJA 109 °C/W t < 10s, note 5 2
Thermal Resistance, Junction to Ambient RϴJA 102 °C/W Steady state, note 6 2
Thermal Resistance, Junction to Ambient RϴJA 71 °C/W t < 10s, note 6 2
Thermal Resistance, Junction to Case RϴJC 34 °C/W note 6 2

CAD (KiCad official)

  • Symbol: DMG6602SVT-7
  • Footprint: Package_TO_SOT_SMD:TSOT-23-6
  • 3D model: TSOT-26 (KiCad packages3D, STEP)
  • 3D model files: dmg6602svt-7-etched.step / dmg6602svt-7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dmg6602svt-7.step / dmg6602svt-7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Diodes Incorporated datasheet (10 pp, sha256 cd7065b693c48e9d, retrieved 2026-09-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF