DAC7563TDGSR

{
  "slug": "dac7563tdgsr",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments Digital To Analog Converters (DAC), VSSOP-10-0.5mm. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
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    "data acquisition",
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  "component": {
    "mpn": "DAC7563TDGSR",
    "manufacturer": "Texas Instruments",
    "package": "VSSOP-10-0.5mm",
    "pin_count": 10,
    "category": "Data Acquisition",
    "subcategory": "Digital To Analog Converters (DAC)",
    "datasheet": "https://www.ti.com/cn/lit/gpn/dac8162t",
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      "lbr": "dac7563tdgsr.lbr"
    },
    "distributor_links": {
      "lcsc": "C2879196",
      "digikey": "296-43287-2-ND",
      "mouser": "595-DAC7563TDGSR"
    },
    "distributor_check": {
      "checked_at": "2026-10-03T04:15:39Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "296-43287-2-ND",
        "status": "found",
        "lifecycle": "Active"
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        "pn": "595-DAC7563TDGSR",
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    },
    "pins": [
      {
        "number": "1",
        "name": "VOUTA",
        "type": "output",
        "description": "Analog output voltage from DAC-A."
      },
      {
        "number": "2",
        "name": "VOUTB",
        "type": "output",
        "description": "Analog output voltage from DAC-B."
      },
      {
        "number": "3",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference point for all circuitry on the device."
      },
      {
        "number": "4",
        "name": "LDAC",
        "type": "input",
        "description": "In synchronous mode, must be connected to GND or held low; in asynchronous mode, used as negative edge-triggered timing signal for simultaneous DAC updates."
      },
      {
        "number": "5",
        "name": "CLR",
        "type": "input",
        "description": "Asynchronous clear input, falling-edge sensitive; loads mid-scale to input and DAC registers; exits clear mode on 24th falling edge of next write."
      },
      {
        "number": "6",
        "name": "SYNC",
        "type": "input",
        "description": "Level-triggered (active-low) frame synchronization input; enables input shift register; DAC output updates on 24th SCLK falling edge; rising edge before 23rd clock acts as interrupt."
      },
      {
        "number": "7",
        "name": "SCLK",
        "type": "input",
        "description": "Serial clock input with Schmitt-trigger logic; data transfer at rates up to 50 MHz."
      },
      {
        "number": "8",
        "name": "DIN",
        "type": "input",
        "description": "Serial data input with Schmitt-trigger logic; data clocked into 24-bit shift register on each SCLK falling edge."
      },
      {
        "number": "9",
        "name": "AVDD",
        "type": "power_in",
        "description": "Power-supply input voltage; recommended supply range 2.7V to 5.5V."
      },
      {
        "number": "10",
        "name": "VREFIN/VREFOUT",
        "type": "bidirectional",
        "description": "Bidirectional voltage reference pin; provides 2.5V output when internal reference is used; can provide or absorb up to 20mA."
      }
    ],
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      "factory_chain": {
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        "primary_model": "claude-haiku-4-5-20251001",
        "primary_mode": "text",
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        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [],
        "pages_sent": 13,
        "cost_usd": 0.1517,
        "at": "2026-10-03T04:15:17"
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      "datasheet": {
        "url": "https://www.ti.com/cn/lit/gpn/dac8162t",
        "pages": 63,
        "sha256": "c924f9150c60d73e",
        "source_tier": "lcsc"
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      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 10,
        "described": 10,
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