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Name	Last commit message	Last updated
docs	Publish 0.1.0 · Ray	3d ago
viewers	dac7563tdgsr: viewers · Ray	3d ago
dac7563tdgsr-etched.glb	dac7563tdgsr: factory component page (tier=lcsc) · Ray	3d ago
dac7563tdgsr-etched.step	dac7563tdgsr: factory component page (tier=lcsc) · Ray	3d ago
dac7563tdgsr-hero.glb	Publish 0.1.0 · Ray	3d ago
dac7563tdgsr-hero.overlay.json	Publish 0.1.0 · Ray	3d ago
dac7563tdgsr.glb	Publish 0.1.0 · Ray	3d ago
dac7563tdgsr.kicad_mod	Publish 0.1.0 · Ray	3d ago
dac7563tdgsr.kicad_sym	Publish 0.1.0 · Ray	3d ago
dac7563tdgsr.lbr	Publish 0.1.0 · Ray	3d ago
dac7563tdgsr.step	Publish 0.1.0 · Ray	3d ago
package.json	dac7563tdgsr: LCSC part number C2879196 (was published as the bare integer) · Ray	7h ago
page.json	dac7563tdgsr: LCSC part number C2879196 (was published as the bare integer) · Ray	7h ago
README.md	Initial commit: component/dac7563tdgsr · Ray	3d ago

DAC7563TDGSR

Texas Instruments · Digital To Analog Converters (DAC) · VSSOP-10-0.5mm

DAC7563TDGSR from Texas Instruments, in a VSSOP-10-0.5mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VOUTA	output	Analog output voltage from DAC-A.
2	VOUTB	output	Analog output voltage from DAC-B.
3	GND	power_in	Ground reference point for all circuitry on the device.
4	LDAC	input	In synchronous mode, must be connected to GND or held low; in asynchronous mode, used as negative edge-triggered timing signal for simultaneous DAC updates.
5	CLR	input	Asynchronous clear input, falling-edge sensitive; loads mid-scale to input and DAC registers; exits clear mode on 24th falling edge of next write.
6	SYNC	input	Level-triggered (active-low) frame synchronization input; enables input shift register; DAC output updates on 24th SCLK falling edge; rising edge before 23rd clock acts as interrupt.
7	SCLK	input	Serial clock input with Schmitt-trigger logic; data transfer at rates up to 50 MHz.
8	DIN	input	Serial data input with Schmitt-trigger logic; data clocked into 24-bit shift register on each SCLK falling edge.
9	AVDD	power_in	Power-supply input voltage; recommended supply range 2.7V to 5.5V.
10	VREFIN/VREFOUT	bidirectional	Bidirectional voltage reference pin; provides 2.5V output when internal reference is used; can provide or absorb up to 20mA.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VSSOP-10-0.5mm
Category	Data Acquisition
Pins	10

CAD (KiCad official)

Symbol: DAC7563TDGSR
Footprint: Package_SO:MSOP-10_3x3mm_P0.5mm
3D model: VSSOP-10-0.5mm (KiCad packages3D, STEP)
3D model files: dac7563tdgsr-etched.step / dac7563tdgsr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dac7563tdgsr.step / dac7563tdgsr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (63 pp, sha256 c924f9150c60d73e, retrieved 2026-10-03, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF