Codex
Public Made by Adomby adom
Codex in Adom Hydrogen: ecosystem setup, dock dashboard and live engineering demos.
d007dad
28d ago
BMS routing: what Astra calculated and checked
This run uses the public Adom BQ76952 BMS Molecule v2. The original project is preserved. Astra calculated new geometry from the schematic, pads, nets, footprint shapes, holes, keepouts and previously accepted copper. No Freerouting or other external autorouter supplied the paths.
Actual saved replay after refill, shown in native KiCad with inactive layers dimmed.
Design basis
The user specified Adom copper ablation, an intended 48 V battery pack and a 72 V / 6 A design basis. The existing four copper layers, each 35 micrometres thick, remain. Vias are permitted. The stated 0.1 mm ablation kerf is not treated as an electrical isolation rule: large power regions use 0.6 mm clearance, and ordinary signal/pin routing retains 0.2 mm clearance. Short dense pin escapes can be 0.15 mm wide.
Plating thickness, acceptable temperatures, enclosure/cooling, operating transients and the complete insulation environment remain physical-design inputs. Neither trace width nor copper coverage establishes a current or temperature rating by itself.
Engineering decisions visible in the progression
| Decision | Why it matters |
|---|---|
| H/V/45-degree routes | All generated segment endpoints pass an eight-direction angle audit. This includes dense pin escapes and later repairs. |
| Joint pin escapes | Neighboring fine-pitch controls are planned together; independently clear escapes can collide when combined. Displaced trunks are restored before acceptance. |
| Local decoupling | C68 and the MCU supply pin were connected to each other but isolated from the supply trunk. Rerouting a blocking LED line allowed a short supply via into the existing inner-layer supply. Duplicating the local capacitor trace would not fix that isolation. |
| Separate grounds | VSS, PGND and QGND retain their distinct net identities and net-tie topology. The shunt's Kelvin filter branches are preserved. |
| Broad load return | A REGIN trace had split the front-layer PGND pour. Moving that trace between existing vias onto In1.Cu restored the return. A single small stitching via was rejected as an inadequate way to address a 6 A path. |
| Correct thermal nets | Fitted Q8/Q9 share /FETs/CD drain copper. The exposed pads on U2/U3/U4 belong to the 12P/8P/4P cell domains, not ground. |
| Assembly variants | Q2, Q3, Q6 and Q7 are DNP; F1 is also DNP in the inspected assembly data. The run preserves the circuit and does not count unpopulated FETs as parallel current paths. Assembly and protection choices must be resolved before building the board. |
| USB review | The candidate uses paired B.Cu trunks with controlled geometric spacing, short front-layer escapes and two transitions per leg. Existing connector branches remain an interface-review concern. This is not measured or field-solved USB impedance qualification. |
| Stricter review | Enabling inherited ignored checks caught one new SCL track through a fiducial keepout. The detour was repaired. Eleven redundant vias and associated dead/duplicate track branches were removed, then native validation was repeated. |
At 6 A, the 1 milliohm shunt's ideal resistive loss is 36 mW. Using the selected MOSFET's 16 milliohm resistance limit at 10 V gate drive gives a conditional 0.576 W conduction estimate for each fitted device before temperature and switching effects. These are calculations, not measured operating losses. See the Infineon device page and TI BQ76952 documentation.
Q8/Q9 share the drain heat-spreading net. Unpopulated alternatives remain in the footprint layout.
The monitor and shunt region after routing and native refill. Copper on inactive layers is dimmed, not removed.
The controller region shows deliberate 45-degree routing and filled regions. USB electrical qualification remains separate.
What the checks establish
The final calculated candidate has 2,326 segments, 343 vias and 30 copper zones. Native KiCad refill and uncapped connectivity report zero unconnected items. The inherited project rules report zero violations. The original human board also has zero opens and zero reported violations under those inherited settings.
A separate diagnostic comparison enables keepout checks, dangling-via checks and solder-mask bridge checks, with 0.2 mm minimum clearance and 0.15 mm minimum track width. After the repairs, the candidate has the same four inherited fiducial-pad keepout errors as the original. The final saved replay has 71 mask-bridge item reports at the six existing spark-gap footprints, also 71 on the original. The separately serialized planning candidate reported 74. These report counts depend on how tracks and pad items intersect the intentionally open spark-gap mask regions; they are not a count of newly introduced shorts. Their assembly and process implications still need review. No dangling-via or dangling-track warnings remain in this stricter candidate report.
The source schematic's ERC has 912 inherited reports. Comparing exported schematic and PCB net membership found no membership differences; 62 name differences are KiCad slash-escaping representations. Routing does not repair or sign off the original schematic's ERC and assembly issues.
The restored PGND front-layer corridor has at least 6.56 mm total filled copper width across sampled horizontal sections from y = -75 to -103 mm within x = 52 to 66 mm, sampled every 0.5 mm. This is a local geometric cross-section check. It does not prove current sharing across every via, complete route resistance, or a temperature limit.
Physical load, fault/transient, thermal and USB testing remain separate. The film demonstrates calculated routing, electrical review decisions and native replay validation, not a production-qualified battery system.
Exact role of Adom Bridge
Astra supplies the plan. kicad_routing_state supplies live board state and revisions. kicad_remove_route removes the original traces/vias in batches of at most 1,024 items. kicad_route_net commits the calculated per-net paths with expectedRevision; these recorded commits use validate:false because the full candidate was checked beforehand. This does not establish that every intermediate prefix passes DRC.
Adom Bridge run_script executes task-owned helpers using native KiCad IPC to remove original board copper graphics/zones, apply the reviewed cleanup, create the 30 new zones and refill/save. It does not patch or replace the installed bridge. kicad_routing_validate checks the live replay, and a separate native CLI check verifies the saved board. desktop_record_window_start and desktop_record_window_stop capture the actual editor; Bridge file transfers bring footage into Hydrogen and return finished MP4s to the user's Windows player.
The recorded process includes an initial accepted routing plan and a final, separately validated refinement before zone creation. Both are visible native edits. The final board is checked again after replay. Original takes, call timestamps, source intervals, playback speeds, narration and edit manifests are retained.
Reusable guidance for Adom users
The released KiCad Bridge package includes general routing, fabrication and review workflows. The Codex package adds codex-adom-electrical-routing, desktop artifact delivery and recording/narration guidance. Installing these packages gives future conversations discoverable instructions; it does not inject new instructions into an already running conversation or bundle a universal autorouter.
The lessons apply beyond this board: inspect actual thermal nets and assembly variants, reserve shared-current returns, plan dense escapes jointly, use real connected components, compare stricter rules against the original, remove redundant copper and validate the actual saved replay. Board-specific paths and load assumptions must be recalculated.
Reproduction prerequisites and prompt · Detailed films and progression.
# BMS routing: what Astra calculated and checked
This run uses the public [Adom BQ76952 BMS Molecule v2](https://wiki.adom.inc/adom/molecule-bq76952-v2). The original project is preserved. Astra calculated new geometry from the schematic, pads, nets, footprint shapes, holes, keepouts and previously accepted copper. No Freerouting or other external autorouter supplied the paths.
Actual saved replay after refill, shown in native KiCad with inactive layers dimmed.
## Design basis
The user specified Adom copper ablation, an intended 48 V battery pack and a 72 V / 6 A design basis. The existing four copper layers, each 35 micrometres thick, remain. Vias are permitted. The stated 0.1 mm ablation kerf is not treated as an electrical isolation rule: large power regions use 0.6 mm clearance, and ordinary signal/pin routing retains 0.2 mm clearance. Short dense pin escapes can be 0.15 mm wide.
Plating thickness, acceptable temperatures, enclosure/cooling, operating transients and the complete insulation environment remain physical-design inputs. Neither trace width nor copper coverage establishes a current or temperature rating by itself.
## Engineering decisions visible in the progression
| Decision | Why it matters |
| --- | --- |
| H/V/45-degree routes | All generated segment endpoints pass an eight-direction angle audit. This includes dense pin escapes and later repairs. |
| Joint pin escapes | Neighboring fine-pitch controls are planned together; independently clear escapes can collide when combined. Displaced trunks are restored before acceptance. |
| Local decoupling | C68 and the MCU supply pin were connected to each other but isolated from the supply trunk. Rerouting a blocking LED line allowed a short supply via into the existing inner-layer supply. Duplicating the local capacitor trace would not fix that isolation. |
| Separate grounds | VSS, PGND and QGND retain their distinct net identities and net-tie topology. The shunt's Kelvin filter branches are preserved. |
| Broad load return | A REGIN trace had split the front-layer PGND pour. Moving that trace between existing vias onto In1.Cu restored the return. A single small stitching via was rejected as an inadequate way to address a 6 A path. |
| Correct thermal nets | Fitted Q8/Q9 share `/FETs/CD` drain copper. The exposed pads on U2/U3/U4 belong to the 12P/8P/4P cell domains, not ground. |
| Assembly variants | Q2, Q3, Q6 and Q7 are DNP; F1 is also DNP in the inspected assembly data. The run preserves the circuit and does not count unpopulated FETs as parallel current paths. Assembly and protection choices must be resolved before building the board. |
| USB review | The candidate uses paired B.Cu trunks with controlled geometric spacing, short front-layer escapes and two transitions per leg. Existing connector branches remain an interface-review concern. This is not measured or field-solved USB impedance qualification. |
| Stricter review | Enabling inherited ignored checks caught one new SCL track through a fiducial keepout. The detour was repaired. Eleven redundant vias and associated dead/duplicate track branches were removed, then native validation was repeated. |
At 6 A, the 1 milliohm shunt's ideal resistive loss is 36 mW. Using the selected MOSFET's 16 milliohm resistance limit at 10 V gate drive gives a conditional 0.576 W conduction estimate for each fitted device before temperature and switching effects. These are calculations, not measured operating losses. See the [Infineon device page](https://www.infineon.com/part/BSC160N15NS5) and [TI BQ76952 documentation](https://www.ti.com/product/BQ76952).
Q8/Q9 share the drain heat-spreading net. Unpopulated alternatives remain in the footprint layout.
The monitor and shunt region after routing and native refill. Copper on inactive layers is dimmed, not removed.
The controller region shows deliberate 45-degree routing and filled regions. USB electrical qualification remains separate.
## What the checks establish
The final calculated candidate has **2,326 segments, 343 vias and 30 copper zones**. Native KiCad refill and uncapped connectivity report **zero unconnected items**. The inherited project rules report **zero violations**. The original human board also has zero opens and zero reported violations under those inherited settings.
A separate diagnostic comparison enables keepout checks, dangling-via checks and solder-mask bridge checks, with 0.2 mm minimum clearance and 0.15 mm minimum track width. After the repairs, the candidate has the same **four inherited fiducial-pad keepout errors** as the original. The final saved replay has **71 mask-bridge item reports at the six existing spark-gap footprints**, also 71 on the original. The separately serialized planning candidate reported 74. These report counts depend on how tracks and pad items intersect the intentionally open spark-gap mask regions; they are not a count of newly introduced shorts. Their assembly and process implications still need review. No dangling-via or dangling-track warnings remain in this stricter candidate report.
The source schematic's ERC has **912 inherited reports**. Comparing exported schematic and PCB net membership found no membership differences; 62 name differences are KiCad slash-escaping representations. Routing does not repair or sign off the original schematic's ERC and assembly issues.
The restored PGND front-layer corridor has at least **6.56 mm total filled copper width** across sampled horizontal sections from y = -75 to -103 mm within x = 52 to 66 mm, sampled every 0.5 mm. This is a local geometric cross-section check. It does not prove current sharing across every via, complete route resistance, or a temperature limit.
Physical load, fault/transient, thermal and USB testing remain separate. The film demonstrates calculated routing, electrical review decisions and native replay validation, not a production-qualified battery system.
## Exact role of Adom Bridge
Astra supplies the plan. `kicad_routing_state` supplies live board state and revisions. `kicad_remove_route` removes the original traces/vias in batches of at most 1,024 items. `kicad_route_net` commits the calculated per-net paths with `expectedRevision`; these recorded commits use `validate:false` because the full candidate was checked beforehand. This does not establish that every intermediate prefix passes DRC.
Adom Bridge `run_script` executes task-owned helpers using native KiCad IPC to remove original board copper graphics/zones, apply the reviewed cleanup, create the 30 new zones and refill/save. It does not patch or replace the installed bridge. `kicad_routing_validate` checks the live replay, and a separate native CLI check verifies the saved board. `desktop_record_window_start` and `desktop_record_window_stop` capture the actual editor; Bridge file transfers bring footage into Hydrogen and return finished MP4s to the user's Windows player.
The recorded process includes an initial accepted routing plan and a final, separately validated refinement before zone creation. Both are visible native edits. The final board is checked again after replay. Original takes, call timestamps, source intervals, playback speeds, narration and edit manifests are retained.
## Reusable guidance for Adom users
The released KiCad Bridge package includes general routing, fabrication and review workflows. The Codex package adds `codex-adom-electrical-routing`, desktop artifact delivery and recording/narration guidance. Installing these packages gives future conversations discoverable instructions; it does not inject new instructions into an already running conversation or bundle a universal autorouter.
The lessons apply beyond this board: inspect actual thermal nets and assembly variants, reserve shared-current returns, plan dense escapes jointly, use real connected components, compare stricter rules against the original, remove redundant copper and validate the actual saved replay. Board-specific paths and load assumptions must be recalculated.
[Reproduction prerequisites and prompt](https://wiki.adom.inc/adom/codex/files/docs/REPRODUCE-KICAD-BMS.md) · [Detailed films and progression](https://wiki.adom.inc/adom/codex/files/docs/ASTRA-KICAD.md).