CD4001UBM96

{
  "schema_version": 1,
  "type": "component",
  "slug": "cd4001ubm96",
  "title": "CD4001UBM96",
  "brief": "Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
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    "logic",
    "cd4001ubm96",
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  "component": {
    "mpn": "CD4001UBM96",
    "manufacturer": "Texas Instruments",
    "package": "SOIC-14",
    "pin_count": 14,
    "category": "Logic",
    "subcategory": "Logic Gates",
    "datasheet": "https://www.ti.com/cn/lit/gpn/cd4001ub",
    "parts": {
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      "footprint": "cd4001ubm96.kicad_mod",
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      "model_3d_step": "cd4001ubm96-etched.step",
      "model_3d_step_plain": "cd4001ubm96.step",
      "lbr": "cd4001ubm96.lbr"
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    "distributor_links": {
      "lcsc": "C2868341"
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    "pins": [
      {
        "number": "1",
        "name": "A",
        "type": "input",
        "description": "Input A to NOR gate 1 (output J = A+B); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 µA at 18 V over the full package-temperature range (100 nA at 18 V, 25°C)."
      },
      {
        "number": "2",
        "name": "B",
        "type": "input",
        "description": "Input B to NOR gate 1 (output J = A+B); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 µA at 18 V over the full package-temperature range (100 nA at 18 V, 25°C)."
      },
      {
        "number": "3",
        "name": "J",
        "type": "output",
        "description": "Output of NOR gate 1 (J = A+B); output low-level voltage max 0.05 V and output high-level voltage min 4.95 V at VDD = 5 V, dissipation per output transistor limited to 100 mW over the full package-temperature range."
      },
      {
        "number": "4",
        "name": "K",
        "type": "output",
        "description": "Output of NOR gate 2 (K = C+D); output low-level voltage max 0.05 V and output high-level voltage min 4.95 V at VDD = 5 V, dissipation per output transistor limited to 100 mW over the full package-temperature range."
      },
      {
        "number": "5",
        "name": "C",
        "type": "input",
        "description": "Input C to NOR gate 2 (output K = C+D); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 µA at 18 V over the full package-temperature range (100 nA at 18 V, 25°C)."
      },
      {
        "number": "6",
        "name": "D",
        "type": "input",
        "description": "Input D to NOR gate 2 (output K = C+D); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 µA at 18 V over the full package-temperature range (100 nA at 18 V, 25°C)."
      },
      {
        "number": "7",
        "name": "VSS",
        "type": "power_in",
        "description": "Negative supply/ground reference for all four NOR gates; DC supply-voltage range (VDD referenced to this pin) is -0.5 V to +20 V absolute maximum, 3 V to 18 V recommended operating range."
      },
      {
        "number": "8",
        "name": "E",
        "type": "input",
        "description": "Input E to NOR gate 3 (output L = E+F); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 µA at 18 V over the full package-temperature range (100 nA at 18 V, 25°C)."
      },
      {
        "number": "9",
        "name": "F",
        "type": "input",
        "description": "Input F to NOR gate 3 (output L = E+F); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 µA at 18 V over the full package-temperature range (100 nA at 18 V, 25°C)."
      },
      {
        "number": "10",
        "name": "L",
        "type": "output",
        "description": "Output of NOR gate 3 (L = E+F); output low-level voltage max 0.05 V and output high-level voltage min 4.95 V at VDD = 5 V, dissipation per output transistor limited to 100 mW over the full package-temperature range."
      },
      {
        "number": "11",
        "name": "M",
        "type": "output",
        "description": "Output of NOR gate 4 (M = G+H); output low-level voltage max 0.05 V and output high-level voltage min 4.95 V at VDD = 5 V, dissipation per output transistor limited to 100 mW over the full package-temperature range."
      },
      {
        "number": "12",
        "name": "G",
        "type": "input",
        "description": "Input G to NOR gate 4 (output M = G+H); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 µA at 18 V over the full package-temperature range (100 nA at 18 V, 25°C)."
      },
      {
        "number": "13",
        "name": "H",
        "type": "input",
        "description": "Input H to NOR gate 4 (output M = G+H); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 µA at 18 V over the full package-temperature range (100 nA at 18 V, 25°C)."
      },
      {
        "number": "14",
        "name": "VDD",
        "type": "power_in",
        "description": "Positive supply pin for all four NOR gates; recommended operating range 3 V to 18 V, absolute maximum -0.5 V to +20 V referenced to VSS."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.2",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.2",
        "primary_model": "claude-sonnet-5",
        "primary_mode": "text+vision",
        "consensus_model": "claude-opus-4-8",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Pin-to-number assignment was read from the functional-diagram and schematic-diagram figures (page 1 ",
          "vision extraction: provenance cannot be text-verified; needs consensus"
        ],
        "pages_sent": 19,
        "cost_usd": 0.6044,
        "at": "2026-09-23T20:08:47"
      },
      "datasheet": {
        "url": "https://www.ti.com/cn/lit/gpn/cd4001ub",
        "pages": 19,
        "sha256": "8bd8a869d467b734",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 14,
        "described": 14,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
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      "footprint": "viewers/footprint.html"
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        "seat": "z = 0",
        "extents_mm": [
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        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "3b9a775da256c8afcc28dcddfbc2eb3f266107fe61ce8446d96f2c52b6f44a70",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
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      {
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        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Texas Instruments",
      "Package": "SOIC-14",
      "Category": "Logic",
      "Pins": "14"
    }
  },
  "variants": [],
  "sections": [
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  "discovery_pitch": "CD4001UBM96 (Texas Instruments) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray"
  },
  "dependencies": {},
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  "visibility": {
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  "updated_at": "2026-09-24T18:36:37.348Z"
}