CD4001UBM96

@@ -53,13 +53,13 @@         "number": "1",         "name": "A",         "type": "input",-        "description": "Input A to NOR gate 1 (output J = A+B); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 \u00b5A at 18 V over the full package-temperature range (100 nA at 18 V, 25\u00b0C)."+        "description": "Input A to NOR gate 1 (output J = A+B); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 µA at 18 V over the full package-temperature range (100 nA at 18 V, 25°C)."       },       {         "number": "2",         "name": "B",         "type": "input",-        "description": "Input B to NOR gate 1 (output J = A+B); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 \u00b5A at 18 V over the full package-temperature range (100 nA at 18 V, 25\u00b0C)."+        "description": "Input B to NOR gate 1 (output J = A+B); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 µA at 18 V over the full package-temperature range (100 nA at 18 V, 25°C)."       },       {         "number": "3",@@ -77,13 +77,13 @@         "number": "5",         "name": "C",         "type": "input",-        "description": "Input C to NOR gate 2 (output K = C+D); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 \u00b5A at 18 V over the full package-temperature range (100 nA at 18 V, 25\u00b0C)."+        "description": "Input C to NOR gate 2 (output K = C+D); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 µA at 18 V over the full package-temperature range (100 nA at 18 V, 25°C)."       },       {         "number": "6",         "name": "D",         "type": "input",-        "description": "Input D to NOR gate 2 (output K = C+D); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 \u00b5A at 18 V over the full package-temperature range (100 nA at 18 V, 25\u00b0C)."+        "description": "Input D to NOR gate 2 (output K = C+D); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 µA at 18 V over the full package-temperature range (100 nA at 18 V, 25°C)."       },       {         "number": "7",@@ -95,13 +95,13 @@         "number": "8",         "name": "E",         "type": "input",-        "description": "Input E to NOR gate 3 (output L = E+F); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 \u00b5A at 18 V over the full package-temperature range (100 nA at 18 V, 25\u00b0C)."+        "description": "Input E to NOR gate 3 (output L = E+F); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 µA at 18 V over the full package-temperature range (100 nA at 18 V, 25°C)."       },       {         "number": "9",         "name": "F",         "type": "input",-        "description": "Input F to NOR gate 3 (output L = E+F); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 \u00b5A at 18 V over the full package-temperature range (100 nA at 18 V, 25\u00b0C)."+        "description": "Input F to NOR gate 3 (output L = E+F); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 µA at 18 V over the full package-temperature range (100 nA at 18 V, 25°C)."       },       {         "number": "10",@@ -119,13 +119,13 @@         "number": "12",         "name": "G",         "type": "input",-        "description": "Input G to NOR gate 4 (output M = G+H); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 \u00b5A at 18 V over the full package-temperature range (100 nA at 18 V, 25\u00b0C)."+        "description": "Input G to NOR gate 4 (output M = G+H); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 µA at 18 V over the full package-temperature range (100 nA at 18 V, 25°C)."       },       {         "number": "13",         "name": "H",         "type": "input",-        "description": "Input H to NOR gate 4 (output M = G+H); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 \u00b5A at 18 V over the full package-temperature range (100 nA at 18 V, 25\u00b0C)."+        "description": "Input H to NOR gate 4 (output M = G+H); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 µA at 18 V over the full package-temperature range (100 nA at 18 V, 25°C)."       },       {         "number": "14",@@ -169,6 +169,46 @@     "viewers": {       "symbol": "viewers/symbol.html",       "footprint": "viewers/footprint.html"-    }+    },+    "models_3d": [+      {+        "file": "cd4001ubm96.step",+        "role": "plain",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          6.0,+          8.7,+          1.75+        ],+        "zmin_mm": -0.0,+        "centre_offset_mm": 0.0,+        "footprint_binding": "identity",+        "sha256": "3b9a775da256c8afcc28dcddfbc2eb3f266107fe61ce8446d96f2c52b6f44a70",+        "checked": "2026-10-07",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      },+      {+        "file": "cd4001ubm96-etched.step",+        "role": "eda",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          6.0,+          8.7,+          1.75+        ],+        "zmin_mm": -0.0,+        "centre_offset_mm": 0.0,+        "footprint_binding": "identity",+        "sha256": "6be0b31495821a61c4788ca5372c7761584071ab08c73d98fab668dd35361af1",+        "checked": "2026-10-07",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      }+    ]   }-}\ No newline at end of file+}