component

CD4001UBM96

Public Made by Adom

by adom

Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogiccd4001ubm96factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

Datasheet

Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

CD4001UBM96

Texas Instruments · Logic Gates · SOIC-14

CD4001UBM96 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A input Input A to NOR gate 1 (output J = A+B); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 µA at 18 V over the full package-temperature range (100 nA at 18 V, 25°C).
2 B input Input B to NOR gate 1 (output J = A+B); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 µA at 18 V over the full package-temperature range (100 nA at 18 V, 25°C).
3 J output Output of NOR gate 1 (J = A+B); output low-level voltage max 0.05 V and output high-level voltage min 4.95 V at VDD = 5 V, dissipation per output transistor limited to 100 mW over the full package-temperature range.
4 K output Output of NOR gate 2 (K = C+D); output low-level voltage max 0.05 V and output high-level voltage min 4.95 V at VDD = 5 V, dissipation per output transistor limited to 100 mW over the full package-temperature range.
5 C input Input C to NOR gate 2 (output K = C+D); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 µA at 18 V over the full package-temperature range (100 nA at 18 V, 25°C).
6 D input Input D to NOR gate 2 (output K = C+D); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 µA at 18 V over the full package-temperature range (100 nA at 18 V, 25°C).
7 VSS power_in Negative supply/ground reference for all four NOR gates; DC supply-voltage range (VDD referenced to this pin) is -0.5 V to +20 V absolute maximum, 3 V to 18 V recommended operating range.
8 E input Input E to NOR gate 3 (output L = E+F); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 µA at 18 V over the full package-temperature range (100 nA at 18 V, 25°C).
9 F input Input F to NOR gate 3 (output L = E+F); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 µA at 18 V over the full package-temperature range (100 nA at 18 V, 25°C).
10 L output Output of NOR gate 3 (L = E+F); output low-level voltage max 0.05 V and output high-level voltage min 4.95 V at VDD = 5 V, dissipation per output transistor limited to 100 mW over the full package-temperature range.
11 M output Output of NOR gate 4 (M = G+H); output low-level voltage max 0.05 V and output high-level voltage min 4.95 V at VDD = 5 V, dissipation per output transistor limited to 100 mW over the full package-temperature range.
12 G input Input G to NOR gate 4 (output M = G+H); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 µA at 18 V over the full package-temperature range (100 nA at 18 V, 25°C).
13 H input Input H to NOR gate 4 (output M = G+H); accepts an input voltage of -0.5 V to VDD+0.5 V and is protected by a CMOS protection network, with maximum input current of 1 µA at 18 V over the full package-temperature range (100 nA at 18 V, 25°C).
14 VDD power_in Positive supply pin for all four NOR gates; recommended operating range 3 V to 18 V, absolute maximum -0.5 V to +20 V referenced to VSS.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category Logic
Pins 14

CAD (KiCad official)

  • Symbol: CD4001UBM96
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: cd4001ubm96-etched.step / cd4001ubm96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4001ubm96.step / cd4001ubm96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (19 pp, sha256 8bd8a869d467b734, retrieved 2026-09-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-sonnet-5 (text+vision), consensus claude-opus-4-8 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF