component
ATTINY402-SSFR
Public Made by Adomby adom
Microchip Tech Microcontrollers (MCU/MPU/SOC), SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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| attiny402-ssfr-etched.step | 9d ago |
| attiny402-ssfr-hero.glb | 9d ago |
| attiny402-ssfr-hero.overlay.json | 9d ago |
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| README.md | 9d ago |
ATTINY402-SSFR
Microchip Tech · Microcontrollers (MCU/MPU/SOC) · SOIC-8
ATTINY402-SSFR from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Supply voltage input; the General Operating Conditions specify VDD from 1.8 V to 5.5 V, and the ATTINY402-SSFR ordering entry lists 2.7 V to 5.5 V at up to 16 MHz. |
| 2 | PA6 | bidirectional | General-purpose I/O pin PA6 that also serves as AIN6 (ADC0), AINN0 (AC0 negative input), TxD (USART0), MOSI (SPI0, alternate position), WO0 (TCA0) and LUT0-OUT (CCL); alternate positions are selected through PORTMUX. |
| 3 | PA7 | bidirectional | General-purpose I/O pin PA7 that also serves as AIN7 (ADC0), AINP0 (AC0 positive input), RxD (USART0), MISO (SPI0, alternate position), WO0 (TCA0, alternate position) and LUT1-OUT (CCL); alternate positions are selected through PORTMUX. |
| 4 | PA1 | bidirectional | General-purpose I/O pin PA1 that also serves as AIN1 (ADC0), TxD (USART0, alternate position), MOSI (SPI0), SDA (TWI0), WO1 (TCA0) and LUT0-IN1 (CCL). |
| 5 | PA2 | bidirectional | General-purpose I/O pin PA2 that also serves as EVOUT0 (Event System output), AIN2 (ADC0), RxD (USART0, alternate position), MISO (SPI0), SCL (TWI0), WO2 (TCA0) and LUT0-IN2 (CCL). |
| 6 | PA0/RESET/UPDI | bidirectional | General-purpose I/O pin PA0 that also serves as the RESET/UPDI pin (configured by RSTPINCFG in FUSE.SYSCFG0), AIN0 (ADC0), XDIR (USART0), SS (SPI0) and LUT0-IN0 (CCL). |
| 7 | PA3/EXTCLK | bidirectional | General-purpose I/O pin PA3 that also serves as the EXTCLK external clock input, AIN3 (ADC0), OUT (AC0 output), XCK (USART0), SCK (SPI0) and WO0/WO3 (TCA0). |
| 8 | GND | power_in | Ground reference for the device. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Embedded Processors & Controllers |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | 2.7 | 5.5 | V | 522 | |||
| Temperature range | -40 | 125 | °C | 522 | |||
| Maximum CPU speed | 16 | MHz | 522 | ||||
| SCK clock frequency (USART SPI master) | fSCK | 10 | MHz | Master | 480 | ||
| SCK period (USART SPI master) | tSCK | 100 | ns | Master | 480 |
CAD (KiCad official)
- Symbol:
ATTINY402-SSFR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
attiny402-ssfr-etched.step/attiny402-ssfr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);attiny402-ssfr.step/attiny402-ssfr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (544 pp, sha256
43193d5174348071, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).