component
ATTINY402-SSFR
Public Made by Adomby adom
Microchip Tech Microcontrollers (MCU/MPU/SOC), SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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},
{
"number": "2",
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},
{
"number": "3",
"name": "PA7",
"type": "bidirectional",
"description": "General-purpose I/O pin PA7 that also serves as AIN7 (ADC0), AINP0 (AC0 positive input), RxD (USART0), MISO (SPI0, alternate position), WO0 (TCA0, alternate position) and LUT1-OUT (CCL); alternate positions are selected through PORTMUX."
},
{
"number": "4",
"name": "PA1",
"type": "bidirectional",
"description": "General-purpose I/O pin PA1 that also serves as AIN1 (ADC0), TxD (USART0, alternate position), MOSI (SPI0), SDA (TWI0), WO1 (TCA0) and LUT0-IN1 (CCL)."
},
{
"number": "5",
"name": "PA2",
"type": "bidirectional",
"description": "General-purpose I/O pin PA2 that also serves as EVOUT0 (Event System output), AIN2 (ADC0), RxD (USART0, alternate position), MISO (SPI0), SCL (TWI0), WO2 (TCA0) and LUT0-IN2 (CCL)."
},
{
"number": "6",
"name": "PA0/RESET/UPDI",
"type": "bidirectional",
"description": "General-purpose I/O pin PA0 that also serves as the RESET/UPDI pin (configured by RSTPINCFG in FUSE.SYSCFG0), AIN0 (ADC0), XDIR (USART0), SS (SPI0) and LUT0-IN0 (CCL)."
},
{
"number": "7",
"name": "PA3/EXTCLK",
"type": "bidirectional",
"description": "General-purpose I/O pin PA3 that also serves as the EXTCLK external clock input, AIN3 (ADC0), OUT (AC0 output), XCK (USART0), SCK (SPI0) and WO0/WO3 (TCA0)."
},
{
"number": "8",
"name": "GND",
"type": "power_in",
"description": "Ground reference for the device."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The datasheet's pinout figure text is garbled, so the pin-number-to-name mapping was taken from Tabl; PA0 is shared with RESET/UPDI; its function depends on the RSTPINCFG fuse (GPIO, UPDI, or RESET). It; Alternate pin positions (marked (3) in Table 5-1) for TxD, RxD, MOSI, MISO and WO0 are selected thro"
],
"pages_sent": 125,
"cost_usd": 0.3616,
"at": "2026-10-17T23:51:20"
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"sha256": "43193d5174348071",
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"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 8,
"described": 8,
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"specs": {
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"Package": "SOIC-8",
"Category": "Embedded Processors & Controllers",
"Pins": "8"
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"source_page": 522,
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{
"name": "Temperature range",
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{
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{
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