ATTINY402-SSFR

{
  "slug": "attiny402-ssfr",
  "version": "0.1.0",
  "type": "component",
  "description": "Microchip Tech Microcontrollers (MCU/MPU/SOC), SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "embedded processors & controllers",
    "attiny402-ssfr",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "attiny402-ssfr.kicad_sym",
    "attiny402-ssfr.kicad_mod",
    "attiny402-ssfr.glb",
    "attiny402-ssfr.step",
    "attiny402-ssfr.lbr",
    "docs/hero.png",
    "docs/attiny402-ssfr-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "attiny402-ssfr-hero.glb",
    "attiny402-ssfr-hero.overlay.json",
    "attiny402-ssfr-etched.glb"
  ],
  "component": {
    "mpn": "ATTINY402-SSFR",
    "manufacturer": "Microchip Tech",
    "package": "SOIC-8",
    "pin_count": 8,
    "category": "Embedded Processors & Controllers",
    "subcategory": "Microcontrollers (MCU/MPU/SOC)",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589932578351312896",
    "parts": {
      "symbol": "attiny402-ssfr.kicad_sym",
      "footprint": "attiny402-ssfr.kicad_mod",
      "model_3d": "attiny402-ssfr-hero.glb",
      "model_3d_plain": "attiny402-ssfr-etched.glb",
      "model_3d_step": "attiny402-ssfr-etched.step",
      "model_3d_step_plain": "attiny402-ssfr.step",
      "lbr": "attiny402-ssfr.lbr"
    },
    "distributor_links": {
      "lcsc": "C2053235"
    },
    "distributor_check": {
      "checked_at": "2026-10-17T23:53:55Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "quota"
      },
      "mouser": {
        "pn": null,
        "status": "quota"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "VDD",
        "type": "power_in",
        "description": "Supply voltage input; the General Operating Conditions specify VDD from 1.8 V to 5.5 V, and the ATTINY402-SSFR ordering entry lists 2.7 V to 5.5 V at up to 16 MHz."
      },
      {
        "number": "2",
        "name": "PA6",
        "type": "bidirectional",
        "description": "General-purpose I/O pin PA6 that also serves as AIN6 (ADC0), AINN0 (AC0 negative input), TxD (USART0), MOSI (SPI0, alternate position), WO0 (TCA0) and LUT0-OUT (CCL); alternate positions are selected through PORTMUX."
      },
      {
        "number": "3",
        "name": "PA7",
        "type": "bidirectional",
        "description": "General-purpose I/O pin PA7 that also serves as AIN7 (ADC0), AINP0 (AC0 positive input), RxD (USART0), MISO (SPI0, alternate position), WO0 (TCA0, alternate position) and LUT1-OUT (CCL); alternate positions are selected through PORTMUX."
      },
      {
        "number": "4",
        "name": "PA1",
        "type": "bidirectional",
        "description": "General-purpose I/O pin PA1 that also serves as AIN1 (ADC0), TxD (USART0, alternate position), MOSI (SPI0), SDA (TWI0), WO1 (TCA0) and LUT0-IN1 (CCL)."
      },
      {
        "number": "5",
        "name": "PA2",
        "type": "bidirectional",
        "description": "General-purpose I/O pin PA2 that also serves as EVOUT0 (Event System output), AIN2 (ADC0), RxD (USART0, alternate position), MISO (SPI0), SCL (TWI0), WO2 (TCA0) and LUT0-IN2 (CCL)."
      },
      {
        "number": "6",
        "name": "PA0/RESET/UPDI",
        "type": "bidirectional",
        "description": "General-purpose I/O pin PA0 that also serves as the RESET/UPDI pin (configured by RSTPINCFG in FUSE.SYSCFG0), AIN0 (ADC0), XDIR (USART0), SS (SPI0) and LUT0-IN0 (CCL)."
      },
      {
        "number": "7",
        "name": "PA3/EXTCLK",
        "type": "bidirectional",
        "description": "General-purpose I/O pin PA3 that also serves as the EXTCLK external clock input, AIN3 (ADC0), OUT (AC0 output), XCK (USART0), SCK (SPI0) and WO0/WO3 (TCA0)."
      },
      {
        "number": "8",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference for the device."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The datasheet's pinout figure text is garbled, so the pin-number-to-name mapping was taken from Tabl; PA0 is shared with RESET/UPDI; its function depends on the RSTPINCFG fuse (GPIO, UPDI, or RESET). It; Alternate pin positions (marked (3) in Table 5-1) for TxD, RxD, MOSI, MISO and WO0 are selected thro"
        ],
        "pages_sent": 125,
        "cost_usd": 0.3616,
        "at": "2026-10-17T23:51:20"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589932578351312896",
        "pages": 544,
        "sha256": "43193d5174348071",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "attiny402-ssfr.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-17",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "attiny402-ssfr-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
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          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "76619a370a39e9331ff3952eaae9dc04f4c6120d31eae1dc95349ceef98fedde",
        "checked": "2026-10-17",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}