component
ADP5071ACPZ-R7
Public Made by Adomby adom
Analog Devices DC-DC Converters, LFCSP-20(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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ADP5071ACPZ-R7
Analog Devices · DC-DC Converters · LFCSP-20(4x4)
ADP5071ACPZ-R7 from Analog Devices, in a LFCSP-20(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | INBK | output | Input disconnect switch output for the boost regulator, with an on resistance of 210 mΩ (typ) per the specifications. |
| 2 | SYNC/FREQ | input | Frequency setting and synchronization input: high sets 2.4 MHz, low sets 1.2 MHz, and an external clock from 1.0 MHz to 2.6 MHz can be connected to synchronize the switching frequency. |
| 3 | SEQ | input | Start-up sequence control: leave open for manual enable, connect to VREG for simultaneous start-up, or pull low for sequenced start-up. |
| 4 | SLEW | input | Driver stage slew rate control for SW1 and SW2: leave open for fastest slew, connect to VREG for normal slew, or connect to AGND for slowest slew. |
| 5 | FB1 | input | Boost regulator feedback input, where a resistor divider from the positive side of COUT1 to AGND programs VPOS; the overvoltage threshold at this pin is 0.86 V (typ). |
| 6 | COMP1 | passive | Error amplifier compensation for the boost regulator, with the compensation network connected between this pin and AGND. |
| 7 | EN1 | input | Boost regulator precision enable, compared to an internal reference with a 1.15 V (typ) high-level threshold and a internal pull-down so the regulator is off when the pin floats. |
| 8 | SS | passive | Soft-start programming: leave open for the fastest soft start, or connect a resistor to AGND to slow the soft start of both regulators. |
| 9 | EN2 | input | Inverting regulator precision enable, compared to an internal reference with a 1.15 V (typ) high-level threshold and an internal pull-down so the regulator is off when the pin floats. |
| 10 | COMP2 | passive | Error amplifier compensation for the inverting regulator, with the compensation network connected between this pin and AGND. |
| 11 | FB2 | input | Inverting regulator feedback input, where a resistor divider from the negative side of COUT2 to VREF programs VNEG. |
| 12 | VREF | power_out | Inverting regulator reference output; connect a 1.0 µF ceramic filter capacitor between VREF and AGND. |
| 13 | AGND | power_in | Analog ground; connect as near to the pin as possible between the CVREF and CVREG capacitors and to the exposed pad. |
| 14 | VREG | power_out | Internal regulator output (4.25 V typ) that needs a 1.0 µF ceramic filter capacitor to AGND and must not be used to supply external circuitry. |
| 15 | PVIN1 | power_in | Power input for the boost regulator, with a supply range of 2.85 V to 15 V. |
| 16 | PVINSYS | power_in | System power supply for the ADP5071, with UVLO rising threshold of 2.85 V (typ) and falling threshold of 2.55 V (typ). |
| 17 | PVIN2 | power_in | Power input for the inverting regulator, with a supply range of 2.85 V to 15 V. |
| 18 | SW2 | output | Switching node for the inverting regulator, rated from PVIN2 − 40 V to PVIN2 + 0.3 V (absolute maximum). |
| 19 | PGND | power_in | Power ground for the boost and inverting regulators, to be kept separate from AGND on the top layer and not connected to the exposed pad on the top layer. |
| 20 | SW1 | output | Switching node for the boost regulator, rated from −0.3 V to +40 V (absolute maximum). |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LFCSP-20(4x4) |
| Category | Power Management (PMIC) |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input supply voltage range (PVIN1, PVIN2, PVINSYS) | VIN | 2.85 | 15 | V | PVIN1, PVIN2, PVINSYS | 3 | |
| Operating quiescent current (PVIN1, PVIN2, PVINSYS total) | IQ | 3.5 | 4 | mA | No switching, EN1 = EN2 = high, PVIN1 = PVIN2 = PVINSYS = 5 V | 3 | |
| Shutdown current | ISHDN | 5 | 10 | µA | No switching, EN1 = EN2 = low, PVIN1 = PVIN2 = PVINSYS = 5 V | 3 | |
| System UVLO threshold PVINSYS, rising | VUVLO_RISING | 2.8 | 2.85 | V | 3 | ||
| System UVLO threshold PVINSYS, falling | VUVLO_FALLING | 2.5 | 2.55 | V | 3 | ||
| Switching frequency (SYNC/FREQ low) | fSW | 1.13 | 1.2 | 1.27 | MHz | SYNC/FREQ = low | 3 |
| Switching frequency (SYNC/FREQ high) | fSW | 2.24 | 2.4 | 2.56 | MHz | SYNC/FREQ = high (connect to VREG) | 3 |
| Input clock range (SYNC/FREQ) | fSYNC | 1 | 2.6 | MHz | 3 | ||
| Input clock minimum on pulse width | tSYNC_MIN_ON | 100 | ns | 3 | |||
| Input clock minimum off pulse width | tSYNC_MIN_OFF | 100 | ns | 3 | |||
| Input clock high logic level | VH (SYNC) | 1.3 | V | 3 | |||
| Input clock low logic level | VL (SYNC) | 0.4 | V | 3 | |||
| Precision enable high level threshold (EN1, EN2) | VTH_H | 1.125 | 1.15 | 1.175 | V | 3 | |
| Precision enable low level threshold (EN1, EN2) | VTH_L | 1.025 | 1.05 | 1.075 | V | 3 | |
| Shutdown mode enable threshold | VTH_S | 0.4 | V | Internal circuitry disabled to achieve ISHDN | 3 | ||
| Feedback voltage accuracy, boost regulator | -0.5 | 0.5 | % | TJ = 25°C | 3 | ||
| Feedback voltage accuracy, boost regulator | -1.5 | 1.5 | % | TJ = −40°C to +125°C | 3 | ||
| Error amplifier transconductance, boost regulator | gM1 | 270 | 300 | 330 | µA/V | 3 | |
| Current-limit threshold, boost regulator | ILIM (BOOST) | 2 | 2.2 | 2.4 | A | 3 | |
| Reference voltage accuracy, inverting regulator | VREF | -0.5 | 0.5 | % | TJ = 25°C | 4 | |
| Reference voltage accuracy, inverting regulator | VREF | -1.5 | 1.5 | % | TJ = −40°C to +125°C | 4 | |
| Feedback voltage accuracy, inverting regulator | -0.5 | 0.5 | % | TJ = 25°C | 4 | ||
| Feedback voltage accuracy, inverting regulator | -1.5 | 1.5 | % | TJ = −40°C to +125°C | 4 | ||
| Error amplifier transconductance, inverting regulator | gM2 | 270 | 300 | 330 | µA/V | 4 | |
| Current-limit threshold, inverting regulator | ILIM (INVERTER) | 1200 | 1320 | 1440 | mA | 4 | |
| Input voltage PVIN1, PVIN2, PVINSYS | -0.3 | 18 | V | 5 | |||
| INBK voltage | -0.3 | V | Maximum printed as PVIN1 + 0.3 V | 5 | |||
| SW1 voltage | -0.3 | 40 | V | 5 | |||
| PGND, AGND voltage | -0.3 | 0.3 | V | 5 | |||
| VREG voltage | VREG | -0.3 | V | Maximum printed as lower of PVINSYS + 0.3 V or +6 V | 5 | ||
| EN1, EN2, FB1, FB2, SYNC/FREQ voltage | -0.3 | 6 | V | 5 | |||
| COMP1, COMP2, SLEW, SS, SEQ, VREF voltage | -0.3 | V | Maximum printed as VREG + 0.3 V | 5 | |||
| Operating junction temperature range | TJ | -40 | 125 | °C | 5 | ||
| Storage temperature range | -65 | 150 | °C | 5 | |||
| Junction-to-ambient thermal resistance, 20-lead LFCSP | θJA | 60.2 | °C/W | 4-layer PCB with nine thermal vias | 5 | ||
| Junction-to-case thermal resistance (top), 20-lead LFCSP | θJC | 36.5 | °C/W | Measured at top of package | 5 | ||
| Junction-to-top characterization parameter, 20-lead LFCSP | ΨJT | 0.63 | °C/W | 5 |
CAD (KiCad official)
- Symbol:
ADP5071ACPZ-R7 - Footprint:
Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm - 3D model: LFCSP-20(4x4) (KiCad packages3D, STEP)
- 3D model files:
adp5071acpz-r7-etched.step/adp5071acpz-r7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);adp5071acpz-r7.step/adp5071acpz-r7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (27 pp, sha256
93df08fe153570f1, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).