ADP5071ACPZ-R7

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  "slug": "adp5071acpz-r7",
  "title": "ADP5071ACPZ-R7",
  "brief": "Analog Devices DC-DC Converters, LFCSP-20(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
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  "component": {
    "mpn": "ADP5071ACPZ-R7",
    "manufacturer": "Analog Devices",
    "package": "LFCSP-20(4x4)",
    "pin_count": 21,
    "category": "Power Management (PMIC)",
    "subcategory": "DC-DC Converters",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588904586980052992",
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    "distributor_links": {
      "lcsc": "C481889"
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      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "quota"
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    "pins": [
      {
        "number": "1",
        "name": "INBK",
        "type": "output",
        "description": "Input disconnect switch output for the boost regulator, with an on resistance of 210 mΩ (typ) per the specifications."
      },
      {
        "number": "2",
        "name": "SYNC/FREQ",
        "type": "input",
        "description": "Frequency setting and synchronization input: high sets 2.4 MHz, low sets 1.2 MHz, and an external clock from 1.0 MHz to 2.6 MHz can be connected to synchronize the switching frequency."
      },
      {
        "number": "3",
        "name": "SEQ",
        "type": "input",
        "description": "Start-up sequence control: leave open for manual enable, connect to VREG for simultaneous start-up, or pull low for sequenced start-up."
      },
      {
        "number": "4",
        "name": "SLEW",
        "type": "input",
        "description": "Driver stage slew rate control for SW1 and SW2: leave open for fastest slew, connect to VREG for normal slew, or connect to AGND for slowest slew."
      },
      {
        "number": "5",
        "name": "FB1",
        "type": "input",
        "description": "Boost regulator feedback input, where a resistor divider from the positive side of COUT1 to AGND programs VPOS; the overvoltage threshold at this pin is 0.86 V (typ)."
      },
      {
        "number": "6",
        "name": "COMP1",
        "type": "passive",
        "description": "Error amplifier compensation for the boost regulator, with the compensation network connected between this pin and AGND."
      },
      {
        "number": "7",
        "name": "EN1",
        "type": "input",
        "description": "Boost regulator precision enable, compared to an internal reference with a 1.15 V (typ) high-level threshold and a internal pull-down so the regulator is off when the pin floats."
      },
      {
        "number": "8",
        "name": "SS",
        "type": "passive",
        "description": "Soft-start programming: leave open for the fastest soft start, or connect a resistor to AGND to slow the soft start of both regulators."
      },
      {
        "number": "9",
        "name": "EN2",
        "type": "input",
        "description": "Inverting regulator precision enable, compared to an internal reference with a 1.15 V (typ) high-level threshold and an internal pull-down so the regulator is off when the pin floats."
      },
      {
        "number": "10",
        "name": "COMP2",
        "type": "passive",
        "description": "Error amplifier compensation for the inverting regulator, with the compensation network connected between this pin and AGND."
      },
      {
        "number": "11",
        "name": "FB2",
        "type": "input",
        "description": "Inverting regulator feedback input, where a resistor divider from the negative side of COUT2 to VREF programs VNEG."
      },
      {
        "number": "12",
        "name": "VREF",
        "type": "power_out",
        "description": "Inverting regulator reference output; connect a 1.0 µF ceramic filter capacitor between VREF and AGND."
      },
      {
        "number": "13",
        "name": "AGND",
        "type": "power_in",
        "description": "Analog ground; connect as near to the pin as possible between the CVREF and CVREG capacitors and to the exposed pad."
      },
      {
        "number": "14",
        "name": "VREG",
        "type": "power_out",
        "description": "Internal regulator output (4.25 V typ) that needs a 1.0 µF ceramic filter capacitor to AGND and must not be used to supply external circuitry."
      },
      {
        "number": "15",
        "name": "PVIN1",
        "type": "power_in",
        "description": "Power input for the boost regulator, with a supply range of 2.85 V to 15 V."
      },
      {
        "number": "16",
        "name": "PVINSYS",
        "type": "power_in",
        "description": "System power supply for the ADP5071, with UVLO rising threshold of 2.85 V (typ) and falling threshold of 2.55 V (typ)."
      },
      {
        "number": "17",
        "name": "PVIN2",
        "type": "power_in",
        "description": "Power input for the inverting regulator, with a supply range of 2.85 V to 15 V."
      },
      {
        "number": "18",
        "name": "SW2",
        "type": "output",
        "description": "Switching node for the inverting regulator, rated from PVIN2 − 40 V to PVIN2 + 0.3 V (absolute maximum)."
      },
      {
        "number": "19",
        "name": "PGND",
        "type": "power_in",
        "description": "Power ground for the boost and inverting regulators, to be kept separate from AGND on the top layer and not connected to the exposed pad on the top layer."
      },
      {
        "number": "20",
        "name": "SW1",
        "type": "output",
        "description": "Switching node for the boost regulator, rated from −0.3 V to +40 V (absolute maximum)."
      },
      {
        "number": "21",
        "name": "EP",
        "type": "passive",
        "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
      }
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      "Package": "LFCSP-20(4x4)",
      "Category": "Power Management (PMIC)",
      "Pins": "21"
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          "name": "Input clock minimum on pulse width",
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          "name": "Input clock minimum off pulse width",
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          "name": "Input clock high logic level",
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          "min": 1.3,
          "typ": null,
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          "name": "Input clock low logic level",
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          "name": "Precision enable high level threshold (EN1, EN2)",
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          "name": "Precision enable low level threshold (EN1, EN2)",
          "symbol": "VTH_L",
          "kind": "electrical",
          "unit": "V",
          "min": 1.025,
          "typ": 1.05,
          "max": 1.075,
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        {
          "name": "Shutdown mode enable threshold",
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          "name": "Error amplifier transconductance, boost regulator",
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          "name": "Reference voltage accuracy, inverting regulator",
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          "name": "Feedback voltage accuracy, inverting regulator",
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          "name": "Error amplifier transconductance, inverting regulator",
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          "name": "Current-limit threshold, inverting regulator",
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